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Capacitive half-bridge with synchronous rectifier

+1 vote

Hello everybody,

I'm trying to simulate the simplified circuit of Capacitive half-bridge with synchronous rectifier, but I always get the error Cyclic behavior during switching. I have tried all the possibilities that Plecs offers online in case of this error, but nothing.

I would be very happy if someone can look at my diagram and tell me what's wrong

I joined two schema, the first (Capacitive half-bridge with synchronous rectifier), which I built in Plecs and the second (Behavior Switch) is the one that indicates how to control the switches and the curve of the current that we should get.

Thank you in advance

asked Apr 7, 2018 by Dirac (21 points)

2 Answers

+4 votes
Best answer

This is a fundamental problem related to the ideal switches and the ideal transformer used in PLECS: Initially T1 and T3 are conducting. When T1 is turned off, PLECS cannot decide whether to turn on the body diode of T2 on the primary side or the body diode of T4 on the secondary side in order to maintain a continuous current through the inductor. Hence the switch bouncing.

To resolve the problem, you need to add transformer leakage so as to decouple the diodes on the primary and secondary side. If you place small inductors (say 1.853e-8 Henries) in series with the two secondary windings (and switch to the stiff RADAU solver), PLECS will properly turn on the body diode of T4 following the turn-off of T1, and the simulation continues...

... but only up to the point where the power flow reverses due to the overshoot of the output capacitor voltage. At this point, when you turn off the gate of T3 while the current flows from drain to source, you are forcibly interrupting the current through the leakage inductor. Hence, PLECS will flag a "State discontinuity" error.

There are several ways to cope with this problem:

  1. Pre-charge the capacitor so as to avoid the voltage overshoot (and hence the power reversal).
  2. Implement a control scheme that will avoid the voltage overshoot or prevent T3 and T4 from being turned on when VDS is positive.
  3. The brute-force method: Place suitably large resistors in parallel with T3 and T4 to provide an alternative path for the current through the leakage inductors.

Attached is a model, in which I have implemented the third method. You can play around with it and verify that the resistors are not necessary if you pre-charge the output capacitor to e.g. 10 Volts.

answered Apr 19, 2018 by Wolfgang Hammer (397 points)
selected Apr 27, 2018 by Dirac

Hello Mr. Wolfgang Hammer

Thank you very much for your detailed explanation

My most distinguished greetings


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0 votes
Changing the "Pulse Delay" block with a "NOT" logic operator makes it work.
answered Apr 10, 2018 by Cata (14 points)