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How can we include parasitic capacitance in MOSFET?

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I'm modelling synchronous Buck Converter in discontinuous conduction mode and I want to check the ringing effect caused due to the parasitic capacitance of semiconductor device. But I'm not able to incorporate this in semiconductor model.
asked Oct 30, 2019 by Pallavi (22 points)
The PLECS power semiconductors are based on ideal switch implementations and are therefore not recommended for device/physical modeling applications. You can add a capacitor across the drain and source (Cds), but the gate input is a control/signal input so the Miller capacitances cannot be directly included. It is possible to develop a custom behavioral model yourself, but this is not trivial.

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