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Switching losses in partially soft-switching inverter

+2 votes
1,352 views
Hello,

I am using PLECS to simulate the losses in an AC/DC inverter.
During an 50Hz sine output period, the inverter is partially soft switching and a part hard switching dependent on the current ripple through the output inductor.
In order to simulate the thermal behavior, I have to add a capacitance across the drain-source of the MOSFETs for soft switching. Also I put some series resistance in there to limit the current through the MOSFET when operated in a hard switching region, also the simulator will throw an error since the voltage across the capacitor jumps from +Udc to zero.
If I would remove the capacitance, I will have some turn-off losses of the FET while it should be ZVS.

This current spike does not significantly influence the conduction losses in the FET since the spike is relatively narrow.
But the thermal model calculates the turn-on and turn-off losses based on amongst others the drain-source voltage and current at the switching instance.
The current spike flowing through the MOSFET does significantly influence the switching losses since the thermal model uses this current spike to determine the switching energy in the lookup table.
Why does PLECS not use the current just before the switching moment to determine the losses?

Is this a known issue and is there a workaround?
An image of the circuit is added.

Thank you for the help!

Best regards,
Bart Bokmans
TU Eindhoven
asked Jun 20, 2018 by bartbokmans (14 points)

1 Answer

+1 vote

Bart,

first off: If you switch at zero voltage (without the capacitors) and still get losses then your loss specifications are probably wrong or incomplete. Please inspect the loss tables and keep in mind that PLECS uses extrapolation (and interpolation) of voltage, current and temperature to determine the losses at a given operating point. If you want to make sure that losses are zero at zero voltage, add a voltage value of 0 V and set all loss values to 0.

If you feel you still have to use the capacitors (which I wouldn't recommend) you are still free to specify how the losses should be calculated. Since the release of PLECS 3.7 you are not limited to voltage, current and temperature as inputs to loss tables anymore but you can specify custom formulas, custom tables, variables and even use custom input signals for loss calculation. If, for example, you create an input signal that is 0 when doing ZVS and 1 otherwise you could simply multiply the result from the lookup table with the value of the input signal, resulting in the ZVS losses being ignored. Please see the section "Adding custom variables" and "Specifying custom variable values" in chapter "Thermal modeling" of the PLECS manual for more details.

Kind regards,

Oliver Schwartz

answered Jun 28, 2018 by Oliver Schwartz (397 points)
Hello Oliver,

Thank you for your answer and sorry for my late response (holiday) but I still don't fully agree.

I will try to explain my problem a little bit better, lets assume I remove these capacitors (in my schematic that I added these are C2...C5). Also lets say that the current through L1 is positive (towards the current source). Switch FET1 is enabled and the current is rising, at some point the switch is going to turn-off. The switch-node voltage is clamped to +Vdc and automatically the diode D2 is going to commutate since the current through the inductor wants to keep running.

With the real converter, the slewrate of the switch-node voltage is limited and will not chance instantaneously. Therefor the voltage across FET1 is approximately equal to 0V and there are no turn-off losses. But since in PLECS the switch-node voltage changes infinitely fast to -Vdc (there is nothing that limits the slewrate such as the capacitors), the simulator thinks the full DC-link voltage is across FET1 and will give turn-off losses for FET1. Although that I already specified in my lookup-table that the turn-off losses are 0J for voltages at 0V.

This I also show in the image that is attached. The current through L1 is positive (see plot 3). The switch-node voltage is at +Vdc and at some point the gate of the highside FET turns-off. The V_SN goes to 0 immediately and thus giving the full DC-Link voltage across FET1 what would normally be 0V since the slewrate of V_SN is limited by the drain-source capacitances and other ones.

Do you understand the problem now that I am encountering?

I have also added an image of the thermal losses lookup tables for your idea.

Bart,

ok, I see your point concerning the capacitors. If I understand you correctly you're happy with the turn-off losses while the capacitors are present. The turn-on losses can't be calculated correctly using the built-in method while the capacitors are present because during turn-on you're basically short-circuiting the capacitor, resulting in a current peak immediately after turn-on.

You could try the following approach:

  • Measure the current through the capacitor. Feed the current into the loss table calculation as, say, i_c. (See my first post for manual reference).
  • Copy your lookup table value for the turn-on losses to a new custom lookup table named, say, "custom_turnon"
  • Change the loss calculation method for the turn-on losses to "Formula".
  • Use Eon=lookup("custom_turnon", v, i-i_c, T) as formula.
The lookup is now performed using the device current minus the current through the capacitor, which should eliminate the influence of the current peak.
 
Kind regards,
 
Oliver Schwartz

 

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