As you may already know, when using a Digital Out to generate a PWM signal the number of possible duty cycles is limited by the discretization step size. In your example with a 5 kHz PWM for a 1usec step size 201 different duty cycles are possible. For a 5usec step size then only 41 different duty cycles are achievable.

For the PWM Out and PWM Out (Variable) blocks, the FPGA is used for carrier generation and so the PWM accuracy is decoupled from the discretization step size. For a 5 kHz PWM on the RT Box 1 ~26,667 different duty cycles are possible.

Therefore, if you cannot reduce the step size to achieve the desired level of accuracy with the Digital Out blocks then the alternative approach would be to dynamically change the frequency, phase, and duty cycle inputs to the PWM Out (Variable) block to replicate the behavior of your modulator.