With PWM Out block, the modulation index (M) is updated with the simulation step, i.e., "fSampling" in your case. However, the digital outputs are refined by the FPGA, enabling the resolution of 7.5 ns. Therefore, PWM edges can occur in between the simulation step.
As given in the "Help" section of the PWM Out block,
with “On carrier minimum” - M will be sampled when the carrier reaches its minimum
with “On carrier maximum” - M will be sampled when the carrier reaches its maximum
with “On carrier minimum/ maximum” - M will be sampled when the carrier reaches its minimum or maximum, whichever comes first -- only once per simulation step
with “Immediately” - M will be updated after each simulation step of the RT Box
Run the attached model to view and compare the results.