The variable step and fixed step are giving different output voltages

Question

I am trying to simulate a model which is attached here. Dead time given is 2us. So when I am using variable step with max step size as 1us, some output voltage is showing in scope while simulating with fixed step size of 0.1us some other output voltage is coming.

So , basically the question is which of the above (variable step or fixed step) is giving the  correct answer(output voltage). My understanding is that the fixed one should give the correct answer, but I dont want to use it because it is taking lot of RAM and slowing down my PC.

Please help

 

 

Answer 1

Whenever you find that the simulation results of a variable-step solver depend on the maximum step size, you should consider that you may have made a modeling mistake regarding the timing of discrete events.

In your model, the problem is your improper usage of the Transport Delay block to delay a discrete pulse train. Please have a look at the note in the online help for this block:

Note  The Transport Delay should not be used to delay non-smooth signals such as rectangular or triangular signals because the solver is not guaranteed to make a simulation step at the precise instants required to accurately reproduce the discontinuities in the delayed signal.

• To generate phase-shifted rectangular or triangular signals, use the Pulse Generator or the Triangular Wave Generator and set the Phase delay parameter appropriately.
• To delay arbitrary signals that only change at discrete instants, use the Pulse Delay.

So, to fix your model,

• replace the Transport Delay blocks with Pulse Delay blocks,
• set the Max step size parameter of the variable-step solver to something large (e.g. "1"),
• (optional, to get smoother looking curves) set the Refine factor to e.g. "10".

Comments

But the advantage of transport delay is that we can feed the variable delay which is needed in closed loop as in the example i have attached.

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Neither the Transport Delay nor the Pulse Delay block in PLECS can model a variable delay.

You are probably thinking of the Variable Time Delay block in Simulink. Like the Transport Delay, this block is meant to delay continuous signals and it is totally inappropriate for delaying pulse trains.

If you want to implement a Phase Shift Modulator, please have a look at the implementation in the demo model "Dual Active Bridge Converter" that ships with PLECS starting with version 4.2.