This is a limitation of the sub-step event power module. From the component documentation:
> The module is implemented with controlled current sources, on both primary and secondary terminals, instead of ideal switches. Both sides of the converter have current source behavior and must be connected to positively biased capacitors or voltage sources.
As you noted, if you remove R1, then the above condition is met.
One idea that might be worthwhile to explore - what if you place a relatively small capacitor (without an ESR) in parallel with your existing capacitor such that Xc,par << XC,esr + Resr? This will allow you to meet the condition to not have an algebraic loop, while still modeling the ESR. You might have to experiment with the Xc,par value to find one that has a minimal impact on the circuit response and is stable for Code Generation.
It is up to you to determine if removing R1 or adding a parallel capacitor is the preferred solution for your application.