Please take a minute to review and accept our Terms of Use.
Welcome to the PLECS User Forum, where you can ask questions and receive answers from other members of the community.

Many technical questions regarding PLECS are answered on the Technical Solutions page of our website. Tutorial videos, specific application examples, and pre-recorded webinars are available on our YouTube page. Please follow us on LinkedIn for the latest Plexim news.

PWM signal in f28049c card using C2000 code generator

0 votes
949 views
Hello,

I am trying to implement a code in my f28049c to control the TI boostxl-buckconv card (a synchronous buck converter). I wanted to do a test asking for two GPIO to input a square wave (pulse generation block) to the mosfets at a frequency of 20 kHz with a duty cycle of 0.5 and discretization period of 5e-6 s. I am measuring the gate signal with an oscilloscope and could not see any signal. If I implement a signal of 10 kHz with a discretization of 1e-5 it is working but every time the discretization is less than 1e-5s I could not get any gating signal. Does anybody have a solution to that or ran through this issue? I need to implement an MPC control algorithm with at least a sampling of 25e-6 s(40 kHz).

 

Best,

T. Harzig
asked Apr 26, 2021 by T. Harzig (12 points)

1 Answer

+1 vote

Hi Harzig,

I was not able to implement a step size of 5e-6 seconds (200 kHz) either, I think it is too fast for this controller. However a sample step size of 12.5e-6 seconds (80 kHz) seems to work.

I implemented the attached model on a 280049C launchpad. There are two subsystems. The subsystem labeled "280049_pwm" is using a PWM block instead of the digital outs. The advantage of this implementation is that irrespective of the duty cycle value, you can have a sample step-size same as the switching period.


The subsystem labeled "280049_digital" is using a pulse generator block. The disadvantage here is that you need to consider the duty cycle value in the sample step-size. For example, for a switching frequency of 40e3 and duty cycle of 0.5, the sample step size must be an integer multiple of 0.5/40e3.

If you want to further discuss your controller implementation, email us at support@plexim.com.

Regards,
Manu

answered Apr 27, 2021 by Manu Parimi (363 points)
Hello Manu,

Thank you for your answer and for the simulation you just sent me. I implemented my control scheme on the card and I noticed couple issues (with a sampling period of 25 us). When I run the external mode on my laptop I notice that the CPU load block display a value of 80 and then not long after, my laptop is not capable of detecting the card anymore. Is 80 for CPU load too much ?

Also, using a simulation of the synchronous buck I managed to draw what I am supposed to have for the gate signals. When comparing the simulation results to the actual the gate signals I have something way different and it seems that the controller stops working.

You will see in the attached file that i kept the LED blinking in a task and the control scheme in another. I set up the multi tasking mode (to separate the blinking from the actual controller scheme). Can this have an impact on how the gate signals are sent to the MOSFET ?

Sorry for the late answer

Best,

Thibaut Harzig
...