Please take a minute to review and accept our Terms of Use.
Welcome to the PLECS User Forum, where you can ask questions and receive answers from other members of the community.

Many technical questions regarding PLECS are answered on the Technical Solutions page of our website. Tutorial videos, specific application examples, and pre-recorded webinars are available on our YouTube page. Please follow us on LinkedIn for the latest Plexim news.

Problem With 3-phase PLL in a 12 pulse thyristor rectifer

0 votes
Hello, I have a problem with my simulation. As we know a 12 pulse igbt rectifier with a fire angle equal to zero have phase shift between voltage and current equal to zero in AC side, but in the simulation I have about 30° between them.

Maybe i have not finished understanding how 3-phase PLL works.

Thank you in advance.
asked Oct 6, 2021 by Alberto Rehbein (21 points)
retagged Oct 18, 2021 by Alberto Rehbein
Hello, can you provide a reference for what waveforms you expect to see here? The model looks like it is working correctly so it would be helpful to better understand the target operation.

Hi Kris, thank you for answering.

This is a picture of one phase of the source when a 12 pulse bridge diode is operating. Here we can see that there is not delay between current (yellow) and voltage (green). 

I expect the same behavior of 12 pulse rectifier using thyristors with fire angle equal to zero, but i have the image below where we clearly see that there is a delay between voltage and current. 


Hi again. This is helpful. Are you able to include the model of the diode rectifier version? And what Scope (name) is the second image from in the model you already provided? Thanks.
Here it is, the model of the second image.

You can see the waveforms on the scope called "Fuentes AC".  The only difference between the models is the rectifier block.

1 Answer

0 votes
Best answer
Alberto, thanks for following up with my colleague Kris.  Please take a look at the attached model, which gives an identical result between the diode and thyristor implementation (apart from thyristor startup).  The 3ph diode/thryistor component is setup as a configurable subsystem so you can benchmark the two results easily in the same model.

When using the PLL block, it's important to understand the phase alignment / 0 degree convention from the PLL.  The transformation used in the PLL from PLECS results in the 0 degrees position aligning with the peak of the phase A voltage (cos(phi) behavior).  I assume in your reference the 0 degree position is aligned with the positive zero crossing (sin(phi) behavior).  Take a look at the "Phase Alignment" scope.  That would explain the 90 degree phase shift in current from what you would expect.

Another minor adjustment one could make in this model is to place the PLL on the primary Y winding opposed to the secondaries. In this simple model there's less voltage harmonics on the primary which can influence the PLL performance.  The delta winding phase is calculated by phase shifting the PLL angle of the primary.
answered Oct 18, 2021 by Bryan Lieblick (1,995 points)
selected Oct 18, 2021 by Alberto Rehbein
Bryan, thank you for the explanation. That helps me a lot.