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Turn-on delay circuit construction

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Hi!

Instead of simply using a turn-on delay block in the library, I would like to find out how turn-on delay circuit is physically constructed and what its components are. One way is to implement a RC delay circuit after the pulse generator, using the time it needs to rise from 0 to 1 as the turn-on delay time, connecting its output and the original PWM waveform to the AND gate input. However, the operation of AND gate does not satisfy the need as it still output 1 during the rise time of the delayed output, so may I ask if there is another way of constructing the turn-on delay circuit in PLECS? (I also checked the inner structure of the turn-on delay block in PLECS, but that does not show the practical way of implementation.) Thank you.

The picture contains the waveform after the AND gate at the top and the waveform after RC delay at the bottom, ideally the top waveform should only become 1 as soon as the bottom waveform rises to 1.

Regards

Haochen Tao
asked Dec 12, 2021 by Haochen Tao (14 points)

1 Answer

0 votes
The logical blocks in PLECS treat any input signal that is not 0 as a logic 1. If you want to trigger the AND block at a certain voltage level you need an additional compare block between your voltmeter and the AND block, e.g. a "Compare to constant" block.

Why you would like to implement a turn-on delay in this way is beyond me. It won't work correctly for high switching frequencies and is computational much more expensive than simply using the turn-on delay block.
answered Dec 16, 2021 by Oliver Schwartz (401 points)
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