As discussed with your last post- the data provided by the manufacturer in the .xml files is the result of their test measurements or calculations, and includes important effects like temperature-dependence. The equations you are using are static and do not take into account such factors as the real hardware (rise time and fall time will depend on the actual gate drive circuitry not just the nominal value in the datasheet) or the influence of temperature. If you really want to isolate the various loss sources in the calculation, though, and look at the differences, you should breakout the switching and conduction losses for each switch and compare them. It looks like, for example, the upper switch has almost triple the conduction loss via your calculation than the measured value (7.5mW vs. 2.3mW, approximated), and for the lower switch 30% less with your calculation (0.35W vs. 0.49W). Likewise, for switching loss in the upper switch, the calculated value is about a third of the simulated one (~46mW vs ~132mW). I suggest then that you revisit your equations, the constants you are inputting to those equations, etc. to see if you find any additional insight.
Also, the result shown in the bottom right of your schematic is simply 1 - Psemi/10 as a percentage (there is no scaling for the input power). Is this where you were getting the 93% efficiency quoted above? If so, it's basically a nonsense value as is currently designed.
I hope this helps, but I'm honestly not sure exactly what your motivation is for comparing the results of static equations with dynamic simulation output using vetted loss data.