Hello everyone, I just want to ask something about triggered subsystem.
I used this kind of system to simulate a board that works with discrete cycle time.
Let's suppose a simple empty triggered block..Single input, single output.
If I watch the signals, they are perfectly the same. How is it possible?
I try to explain... In every real board, there is always at least one sample delay. Therefore, the output should be shifted at least by one sample delay compared to input. Am I wrong?
How can I consider this delay? Just with a zero-holder or there is a specific subsystem to achieve this?
I hope to have made myself quite clear.