Sub-cycle averaging consists of averaging all of the individual gate signal inputs and applying that to an integrated model at the power module level. See the "3-Level Half Bridge (T-Type)" power module for an example of a power module which essentially has a bidirectional switch in the neutral path. If there is no analog in the power module library, you will have to derive your own model. What topology are you modeling?
See the introductory paper on sub-cycle averaging and paper on multi-level topologies.
You can use a digital input connected to a switch, but note that sampling a PWM signal once per simulation step the simulation results in poor performance unless the model step size is very small compared to the switching period.