# Latest

**URL:** https://forum.plexim.com/latest.md?page=1

[Latest](https://forum.plexim.com/latest.md) · [Categories](https://forum.plexim.com/categories.md) · [Tags](https://forum.plexim.com/tags.md)

**Page:** 2

---

## [How to change simulation parameter via xml-rpc during simulation?](https://forum.plexim.com/t/how-to-change-simulation-parameter-via-xml-rpc-during-simulation/2857)

<div class="topic-metadata">

**Author:** [@vishweshgm](https://forum.plexim.com/u/vishweshgm)\
**Replies:** 5\
**Last updated:** [August 27, 2026, 7:24am UTC](https://forum.plexim.com/t/how-to-change-simulation-parameter-via-xml-rpc-during-simulation/2857 "2026-08-27T07:24:46Z")

</div>

Hi, I am using python xml-rpc to run simulation and use plecs.simulate() to start simulation. Once simulation start, until it ends, I am unable to send get&set parameter command. However if in model window, if I …

---

## [Turn-on loss for partial ZVS or ZCS converter](https://forum.plexim.com/t/turn-on-loss-for-partial-zvs-or-zcs-converter/3278)

<div class="topic-metadata">

**Author:** [@Kyuyeong](https://forum.plexim.com/u/Kyuyeong)\
**Replies:** 1\
**Last updated:** [August 25, 2026, 6:21am UTC](https://forum.plexim.com/t/turn-on-loss-for-partial-zvs-or-zcs-converter/3278 "2026-08-25T06:21:00Z")

</div>

Hello! I’m trying to make switching loss model for partial ZVS or ZCS converter. I believe achieving ZVS means they don’t have turn-on loss but how about partial ZVS and ZCS converter? I already put it each legend,…

---

## [Dual-CPU targets (F28P65x) – GPIO direction](https://forum.plexim.com/t/dual-cpu-targets-f28p65x-gpio-direction/3277)

<div class="topic-metadata">

**Author:** [@Michael](https://forum.plexim.com/u/Michael)\
**Replies:** 2\
**Last updated:** [August 25, 2026, 4:41am UTC](https://forum.plexim.com/t/dual-cpu-targets-f28p65x-gpio-direction/3277 "2026-08-25T04:41:37Z")

</div>

Digital Output assigned to the secondary CPU never drives the pin (F28P65x dual-core) – bug, or are we missing something? What we are seeing On a dual-core F28P65x, a Digital Output block assigned to the secondary CPU (…

---

## [HERIC Inverter Loss Analysis in PLECS](https://forum.plexim.com/t/heric-inverter-loss-analysis-in-plecs/3276)

<div class="topic-metadata">

**Author:** [@ErickGP](https://forum.plexim.com/u/ErickGP)\
**Replies:** 1\
**Last updated:** [August 24, 2026, 5:40am UTC](https://forum.plexim.com/t/heric-inverter-loss-analysis-in-plecs/3276 "2026-08-24T05:40:42Z")

</div>

I have a question. I am using PLECS 5.0.3 to analyze losses in a HERIC inverter that uses MOSFETs with diodes. To do this, I uploaded the thermal model for the IPW60R041P6 MOSFET and placed a Heat Sink block over the ful…

---

## [Matrix Converter - Cyclic Behaviour](https://forum.plexim.com/t/matrix-converter-cyclic-behaviour/3218)

<div class="topic-metadata">

**Author:** [@eeyml8](https://forum.plexim.com/u/eeyml8)\
**Replies:** 3\
**Last updated:** [August 20, 2026, 5:54pm UTC](https://forum.plexim.com/t/matrix-converter-cyclic-behaviour/3218 "2026-08-20T17:54:58Z")

</div>

Good afternoon, I am currently working on a simulation of a three-phase to three-phase direct matrix converter using the 4-step commutation technique. I am having some difficult with an error that I cannot find the solu…

---

## [Op-Amps and State Space Extraction](https://forum.plexim.com/t/op-amps-and-state-space-extraction/3271)

<div class="topic-metadata">

**Author:** [@HPI\_GHunsicker](https://forum.plexim.com/u/HPI_GHunsicker)\
**Replies:** 5\
**Last updated:** [August 19, 2026, 9:07am UTC](https://forum.plexim.com/t/op-amps-and-state-space-extraction/3271 "2026-08-19T09:07:04Z")

</div>

I’m trying to extract the state space of a filter containing an op-amp and I’m consistently getting a state space that is equivalent in offset but with a smaller amplitude. I used the state\_space\_matrices example to set …

---

## [Question about MOSFET switching loss with external Coss and custom commutation current in PLECS 4.7.4](https://forum.plexim.com/t/question-about-mosfet-switching-loss-with-external-coss-and-custom-commutation-current-in-plecs-4-7-4/3264)

<div class="topic-metadata">

**Author:** [@Kris](https://forum.plexim.com/u/Kris)\
**Replies:** 1\
**Last updated:** [August 10, 2026, 5:52pm UTC](https://forum.plexim.com/t/question-about-mosfet-switching-loss-with-external-coss-and-custom-commutation-current-in-plecs-4-7-4/3264 "2026-08-10T17:52:18Z")

</div>

Hello, I am using PLECS 4.7.4 to simulate an SRDAB converter. The switches use the MOSFET with Diode component together with Infineon thermal descriptions. I added an external Coss across each MOSFET because I want to …

---

## [Positive Negative sequence seperation with DDSRF](https://forum.plexim.com/t/positive-negative-sequence-seperation-with-ddsrf/3261)

<div class="topic-metadata">

**Author:** [@smmuabd1](https://forum.plexim.com/u/smmuabd1)\
**Replies:** 1\
**Last updated:** [August 10, 2026, 5:24pm UTC](https://forum.plexim.com/t/positive-negative-sequence-seperation-with-ddsrf/3261 "2026-08-10T17:24:28Z")

</div>

I am building a cascaded H bridge model for unbalanced conditions and need a positive, negative sequence seperation approach, but any approach I have tried does not work so far are any pre built models or exampes of posi…

---

## [Dual active bridge-cf](https://forum.plexim.com/t/dual-active-bridge-cf/3180)

<div class="topic-metadata">

**Author:** [@AbhishekArragunta](https://forum.plexim.com/u/AbhishekArragunta)\
**Replies:** 11\
**Last updated:** [August 10, 2026, 2:31pm UTC](https://forum.plexim.com/t/dual-active-bridge-cf/3180 "2026-08-10T14:31:14Z")

</div>

DAB.plecs (104.8 KB) i am using this Block to create phase shift but will need some different logic to achieve please suggest any changes can be made so that the Block can be modified to generate the pwm as per the image…

---

## [Processing Bitstream from Delta-Sigma Modulator](https://forum.plexim.com/t/processing-bitstream-from-delta-sigma-modulator/3247)

<div class="topic-metadata">

**Author:** [@sanksan](https://forum.plexim.com/u/sanksan)\
**Replies:** 2\
**Last updated:** [August 7, 2026, 8:44am UTC](https://forum.plexim.com/t/processing-bitstream-from-delta-sigma-modulator/3247 "2026-08-07T08:44:58Z")

</div>

Dear Concerned, I am currently working on a design that uses delta-sigma modulator for measuring different voltage and current signals. These modulator provide a digital bitstream output, which is currently fed to a DSP…

---

## [Carrier-peak synchronized sampling using the PWM Out block on RT Box](https://forum.plexim.com/t/carrier-peak-synchronized-sampling-using-the-pwm-out-block-on-rt-box/3257)

<div class="topic-metadata">

**Author:** [@pimagine](https://forum.plexim.com/u/pimagine)\
**Replies:** 5\
**Last updated:** [August 6, 2026, 3:08pm UTC](https://forum.plexim.com/t/carrier-peak-synchronized-sampling-using-the-pwm-out-block-on-rt-box/3257 "2026-08-06T15:08:04Z")

</div>

Hello, I am implementing a PWM control system on an RT Box using the PWM Out block. In my control algorithm, I need to perform a sampling operation exactly at the positive peak of the triangular carrier used by the PWM …

---

## [How to Generate the Optimal Inner and Outer Phase Shifts for Extended Phase Shift Modulation in a Series Partial-Power Dual Active Bridge Converter?](https://forum.plexim.com/t/how-to-generate-the-optimal-inner-and-outer-phase-shifts-for-extended-phase-shift-modulation-in-a-series-partial-power-dual-active-bridge-converter/3256)

<div class="topic-metadata">

**Author:** [@Arnob](https://forum.plexim.com/u/Arnob)\
**Replies:** 0\
**Last updated:** [August 5, 2026, 4:39am UTC](https://forum.plexim.com/t/how-to-generate-the-optimal-inner-and-outer-phase-shifts-for-extended-phase-shift-modulation-in-a-series-partial-power-dual-active-bridge-converter/3256 "2026-08-05T04:39:23Z")

</div>

Hi everyone, I am working on a series partial-power DAB converter and would like to implement Extended Phase Shift (EPS) modulation. My goal is not just to transfer the required power, but to generate the optimal inner…

---

## [How to quantify the time delay of a RT BOX Controller?](https://forum.plexim.com/t/how-to-quantify-the-time-delay-of-a-rt-box-controller/1248)

<div class="topic-metadata">

**Author:** [@TWY](https://forum.plexim.com/u/TWY)\
**Replies:** 2\
**Last updated:** [August 4, 2026, 6:10am UTC](https://forum.plexim.com/t/how-to-quantify-the-time-delay-of-a-rt-box-controller/1248 "2026-08-04T06:10:37Z")

</div>

In the RT-Box manual, a timing diagram is given as follow. I want to determine the exact time delay in a converter system controlled by a RT-Box 2, so that I can model the system and design the parameters. \*1. In terms …

---

## [Upgrading student licence to a newer version](https://forum.plexim.com/t/upgrading-student-licence-to-a-newer-version/3254)

<div class="topic-metadata">

**Author:** [@bodikiefer](https://forum.plexim.com/u/bodikiefer)\
**Replies:** 1\
**Last updated:** [August 3, 2026, 12:07pm UTC](https://forum.plexim.com/t/upgrading-student-licence-to-a-newer-version/3254 "2026-08-03T12:07:16Z")

</div>

Dear community, My student licence only supports up to version 4.9. Though since I am using Matlab 26, I have upgraded the Plecs Blockset to version 5.0. Would it be possible to upgrade my already existing student licen…

---

## [Assistance with adapting DAB for RTBox HIL](https://forum.plexim.com/t/assistance-with-adapting-dab-for-rtbox-hil/3228)

<div class="topic-metadata">

**Author:** [@Alyssa](https://forum.plexim.com/u/Alyssa)\
**Replies:** 10\
**Last updated:** [July 31, 2026, 3:57pm UTC](https://forum.plexim.com/t/assistance-with-adapting-dab-for-rtbox-hil/3228 "2026-07-31T15:57:28Z")

</div>

Hi there, I am trying to adapt the plant of my DAB for controller HIL. I am using the DAB component found in the component library and the offline simulation runs but when I tried to build to RTBox1 I get the error: The…

---

## [Does PLECS interpolate the loss model between temperatures if the device's thermal model is only provided for certain temperatures?](https://forum.plexim.com/t/does-plecs-interpolate-the-loss-model-between-temperatures-if-the-devices-thermal-model-is-only-provided-for-certain-temperatures/3244)

<div class="topic-metadata">

**Author:** [@plexie](https://forum.plexim.com/u/plexie)\
**Replies:** 2\
**Last updated:** [July 29, 2026, 11:21pm UTC](https://forum.plexim.com/t/does-plecs-interpolate-the-loss-model-between-temperatures-if-the-devices-thermal-model-is-only-provided-for-certain-temperatures/3244 "2026-07-29T23:21:43Z")

</div>

If the device’s thermal model is only provided for certain temperatures, does PLECS linearly interpolate between the temperatures to generate loss calculations for the device when it’s at an unspecified junction temperat…

---

## [Discrepancy between heat flow and conduction loss in thermal model](https://forum.plexim.com/t/discrepancy-between-heat-flow-and-conduction-loss-in-thermal-model/3243)

<div class="topic-metadata">

**Author:** [@plexie](https://forum.plexim.com/u/plexie)\
**Replies:** 6\
**Last updated:** [July 29, 2026, 6:01pm UTC](https://forum.plexim.com/t/discrepancy-between-heat-flow-and-conduction-loss-in-thermal-model/3243 "2026-07-29T18:01:22Z")

</div>

Hi there! I am trying to use a manufacturer’s thermal model for a FET to obtain conduction loss values. I set up a PLECS model similar to what is shown in the picture below (heat sink for a single FET → Rth (case-to-ambi…

---

## [Issue Simulating Infineon CoolSiC MOSFET Models in PLECS 5.0.6](https://forum.plexim.com/t/issue-simulating-infineon-coolsic-mosfet-models-in-plecs-5-0-6/3242)

<div class="topic-metadata">

**Author:** [@Vol](https://forum.plexim.com/u/Vol)\
**Replies:** 2\
**Last updated:** [July 29, 2026, 11:22am UTC](https://forum.plexim.com/t/issue-simulating-infineon-coolsic-mosfet-models-in-plecs-5-0-6/3242 "2026-07-29T11:22:42Z")

</div>

Hi everyone, I’m having trouble simulating some Infineon SiC MOSFET models provided in the following package: Infineon-CoolSiC\_1200V\_Gen2\_Trench\_MOSFET-PLECS-v03\_01 In particular, I’m trying to use: IMBG120R040M2H I…

---

## [Complementary PWMs on different channels STM32](https://forum.plexim.com/t/complementary-pwms-on-different-channels-stm32/3240)

<div class="topic-metadata">

**Author:** [@Davi](https://forum.plexim.com/u/Davi)\
**Replies:** 1\
**Last updated:** [July 28, 2026, 1:24pm UTC](https://forum.plexim.com/t/complementary-pwms-on-different-channels-stm32/3240 "2026-07-28T13:24:47Z")

</div>

Hello, I would like to use the STM32’s PWM block to generate two complementary PWM signals on different channels, rather than generating them on the same channel. I am doing this for a three-phase converter control simul…

---

## [Support for the TMS320F28P551x](https://forum.plexim.com/t/support-for-the-tms320f28p551x/3215)

<div class="topic-metadata">

**Author:** [@caiodasilva05](https://forum.plexim.com/u/caiodasilva05)\
**Replies:** 1\
**Last updated:** [July 27, 2026, 5:26pm UTC](https://forum.plexim.com/t/support-for-the-tms320f28p551x/3215 "2026-07-27T17:26:39Z")

</div>

Hi! TI has recently released the TMS320F28P551x of TI C2000 last year. I am interested in using PLECS Coder for my project involving this line of MCUs. Does PLECS Coder support the F28P551x line? If not, when can we exp…

---

## [Seeking 12-pulse Cycloconverter Reference Model or C-Script for Cosine Intersectional Control](https://forum.plexim.com/t/seeking-12-pulse-cycloconverter-reference-model-or-c-script-for-cosine-intersectional-control/3020)

<div class="topic-metadata">

**Author:** [@Benja](https://forum.plexim.com/u/Benja)\
**Replies:** 1\
**Last updated:** [July 27, 2026, 9:02am UTC](https://forum.plexim.com/t/seeking-12-pulse-cycloconverter-reference-model-or-c-script-for-cosine-intersectional-control/3020 "2026-07-27T09:02:41Z")

</div>

Hi everyone, I am currently developing a simulation in PLECS for a 12-pulse Cycloconverter (CCV) targeted at a high-power mining application (specifically for a 19.6 MW Synchronous Motor drive). While I have the power …

---

## [Simulating Verilog Logic in PLECS via Verilator](https://forum.plexim.com/t/simulating-verilog-logic-in-plecs-via-verilator/3238)

<div class="topic-metadata">

**Author:** [@Munadir\_Ahmed](https://forum.plexim.com/u/Munadir_Ahmed)\
**Replies:** 0\
**Last updated:** [July 23, 2026, 8:18pm UTC](https://forum.plexim.com/t/simulating-verilog-logic-in-plecs-via-verilator/3238 "2026-07-23T20:18:24Z")

</div>

Introduction If your control logic is written in Verilog, headed for an FPGA or ASIC down the line, you’ll eventually want to validate it in PLECS. PLECS can’t run Verilog directly, so the usual options are to hand-trans…

---

## [Why is my conduction loss so low—only 0.9 W?](https://forum.plexim.com/t/why-is-my-conduction-loss-so-low-only-0-9-w/3235)

<div class="topic-metadata">

**Author:** [@YXJ](https://forum.plexim.com/u/YXJ)\
**Replies:** 1\
**Last updated:** [July 23, 2026, 2:42pm UTC](https://forum.plexim.com/t/why-is-my-conduction-loss-so-low-only-0-9-w/3235 "2026-07-23T14:42:12Z")

</div>

TIME2.slx (124.4 KB)

---

## [Glitch in Variable Phase PWM block?](https://forum.plexim.com/t/glitch-in-variable-phase-pwm-block/1343)

<div class="topic-metadata">

**Author:** [@ThoseWhoWish2B](https://forum.plexim.com/u/ThoseWhoWish2B)\
**Replies:** 5\
**Last updated:** [July 21, 2026, 10:41am UTC](https://forum.plexim.com/t/glitch-in-variable-phase-pwm-block/1343 "2026-07-21T10:41:09Z")

</div>

Hello all, I’m using the Variable Phase PWM block to generate PWM signals for 2 full-bridges that are phase-shifted. Within each full-bridge, their half-bridges have 50% duty and are phase-shifted to create a zero vecto…

---

## [I want to add a carrier delay in SVPWM in PLECS demo named three phase voltage source inverter](https://forum.plexim.com/t/i-want-to-add-a-carrier-delay-in-svpwm-in-plecs-demo-named-three-phase-voltage-source-inverter/3224)

<div class="topic-metadata">

**Author:** [@Yu\_Johanna\_Cao](https://forum.plexim.com/u/Yu_Johanna_Cao)\
**Replies:** 3\
**Last updated:** [July 20, 2026, 1:40pm UTC](https://forum.plexim.com/t/i-want-to-add-a-carrier-delay-in-svpwm-in-plecs-demo-named-three-phase-voltage-source-inverter/3224 "2026-07-20T13:40:06Z")

</div>

I want to add a carrier delay, but the mode I cannot edit.

---

## [Assistance with Modified Thermal XML Model for Parallel IGBT Modules](https://forum.plexim.com/t/assistance-with-modified-thermal-xml-model-for-parallel-igbt-modules/3205)

<div class="topic-metadata">

**Author:** [@MilanVdW](https://forum.plexim.com/u/MilanVdW)\
**Replies:** 3\
**Last updated:** [July 19, 2026, 10:57pm UTC](https://forum.plexim.com/t/assistance-with-modified-thermal-xml-model-for-parallel-igbt-modules/3205 "2026-07-19T22:57:55Z")

</div>

Dear PLECS Support Team I have developed an AFE converter model that, in reality, uses the 6 Infineon FS450R17OE4 IGBT module. Due to the high current, each switching position consists of six identical IGBT modules conn…

---

## [Update software to newest version 5.0 , but have some trouble](https://forum.plexim.com/t/update-software-to-newest-version-5-0-but-have-some-trouble/3221)

<div class="topic-metadata">

**Author:** [@Yu\_Johanna\_Cao](https://forum.plexim.com/u/Yu_Johanna_Cao)\
**Replies:** 3\
**Last updated:** [July 18, 2026, 5:35am UTC](https://forum.plexim.com/t/update-software-to-newest-version-5-0-but-have-some-trouble/3221 "2026-07-18T05:35:01Z")

</div>

Error wirting to file://…Verify you have access to that directory.

---

## [Cyclic behavior during switching below D = 0.67 in Quadratic Buck-Boost Converter](https://forum.plexim.com/t/cyclic-behavior-during-switching-below-d-0-67-in-quadratic-buck-boost-converter/3212)

<div class="topic-metadata">

**Author:** [@BurakOzdemir](https://forum.plexim.com/u/BurakOzdemir)\
**Replies:** 3\
**Last updated:** [July 17, 2026, 2:54pm UTC](https://forum.plexim.com/t/cyclic-behavior-during-switching-below-d-0-67-in-quadratic-buck-boost-converter/3212 "2026-07-17T14:54:34Z")

</div>

Hello, I am having a persistent “Cyclic behavior during switching” error in my Quadratic Buck-Boost Converter simulation in PLECS, specifically when the duty cycle falls below 0.67. Above this value, the simulation runs…

---

## [Principle of switch loss of probe module](https://forum.plexim.com/t/principle-of-switch-loss-of-probe-module/1377)

<div class="topic-metadata">

**Author:** [@emma2](https://forum.plexim.com/u/emma2)\
**Replies:** 7\
**Last updated:** [July 17, 2026, 1:35pm UTC](https://forum.plexim.com/t/principle-of-switch-loss-of-probe-module/1377 "2026-07-17T13:35:24Z")

</div>

Hello, I am a new user of plecs, and I have questions about probe’s calculation of switch loss. What is the principle of plecs probe module to calculate the switching loss of the device? According to the official websit…

---

## [Spike Pulses in Variable Phase PWM block](https://forum.plexim.com/t/spike-pulses-in-variable-phase-pwm-block/3222)

<div class="topic-metadata">

**Author:** [@DHQ007](https://forum.plexim.com/u/DHQ007)\
**Replies:** 2\
**Last updated:** [July 17, 2026, 12:25pm UTC](https://forum.plexim.com/t/spike-pulses-in-variable-phase-pwm-block/3222 "2026-07-17T12:25:36Z")

</div>

Hello, when using the Variable Phase PWM block, I found that complementary pulse outputs can be achieved by swapping the block’s Output values parameter. However, the pulse range for the upper arm is 0~4, and the puls…

[Previous page](https://forum.plexim.com/latest.md)

[Next page](https://forum.plexim.com/latest.md?page=2)
