# Flip-flop giving wrong output

**URL:** <https://forum.plexim.com/t/flip-flop-giving-wrong-output/1500>\
**Category:** PLECS\
**Tags:** plecs\
**Created:** [November 8, 2024, 1:04pm UTC](https://forum.plexim.com/t/flip-flop-giving-wrong-output/1500 "2024-11-08T13:04:36Z")\
**Posts on this page:** 2\
**Page:** 1

<div class="post-metadata">

**Author:** ![Aanshy](https://avatars.discourse-cdn.com/v4/letter/a/f17d59/32.png) [@Aanshy](https://forum.plexim.com/u/Aanshy)\
**Post date:** [November 8, 2024, 1:04pm UTC](https://forum.plexim.com/t/flip-flop-giving-wrong-output/1500/1 "2024-11-08T13:04:36Z")

</div>

I have a phase shift modulation scheme designed in PLECS standalone. I am using this model in simulink controller for getting switching signals using PLECS blockset. Weird thing is one of the SR flip-flop in the modulation scheme is giving wrong output. Example, when the inputs are 0 1, it gives 0 when ideally it should give 1. SR flip flop2 at the bottom is generating wrong signals. I don’t understand how this is happening. Can anyone suggest something?

 ![1000128259](https://europe1.discourse-cdn.com/flex006/uploads/plecs/original/2X/1/1b816c18cb386f4b4a800e8fbaf953c8c1f244f7.png)  
 ![1000128257](https://europe1.discourse-cdn.com/flex006/uploads/plecs/original/2X/6/683ce74ce12df756d4b76d63857adcb828f0b5be.png)

---

<div class="post-metadata">

**Author:** ![Bryan\_Lieblick](https://dub1.discourse-cdn.com/flex006/user_avatar/forum.plexim.com/bryan_lieblick/32/10_2.png) [@Bryan\_Lieblick](https://forum.plexim.com/u/Bryan_Lieblick)\
**Post date:** [November 8, 2024, 2:23pm UTC](https://forum.plexim.com/t/flip-flop-giving-wrong-output/1500/2 "2024-11-08T14:23:10Z")

</div>

Please post your model for further support.