# For FPGA simulation, power modules must be connected directly to PWMCapture blocks (input 3, signal 1)

**URL:** <https://forum.plexim.com/t/for-fpga-simulation-power-modules-must-be-connected-directly-to-pwmcapture-blocks-input-3-signal-1/1938>\
**Category:** RT Box\
**Tags:** rt-box\
**Created:** [March 23, 2025, 2:57am UTC](https://forum.plexim.com/t/for-fpga-simulation-power-modules-must-be-connected-directly-to-pwmcapture-blocks-input-3-signal-1/1938 "2025-03-23T02:57:43Z")\
**Posts on this page:** 2\
**Page:** 1

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**Author:** ![Liuhanqing](https://avatars.discourse-cdn.com/v4/letter/l/9de053/32.png) [@Liuhanqing](https://forum.plexim.com/u/Liuhanqing)\
**Post date:** [March 23, 2025, 2:57am UTC](https://forum.plexim.com/t/for-fpga-simulation-power-modules-must-be-connected-directly-to-pwmcapture-blocks-input-3-signal-1/1938/1 "2025-03-23T02:57:43Z")

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how can i solve this problem  
For FPGA simulation, power modules must be connected directly to PWMCapture blocks (input 3, signal 1).

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**Author:** ![Bryan\_Lieblick](https://dub1.discourse-cdn.com/flex006/user_avatar/forum.plexim.com/bryan_lieblick/32/10_2.png) [@Bryan\_Lieblick](https://forum.plexim.com/u/Bryan_Lieblick)\
**Post date:** [March 24, 2025, 1:57pm UTC](https://forum.plexim.com/t/for-fpga-simulation-power-modules-must-be-connected-directly-to-pwmcapture-blocks-input-3-signal-1/1938/2 "2025-03-24T13:57:21Z")

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As the error states, for FPGA based simulation the modulation signals from the PWM capture block must directly connect to the power module gates. You cannot place additional logic (signal switches, boolean operators, etc.) in the signal path.