Shridhara, that is the correct workflow to program the RT Box with the electrical model simulated on the FPGA. When you actually program the RT Box you will see the FPGA step size appear in the RT Box’s physical display as well as in the RT Box web interface.
Regarding the generated code, the PLECS Coder does not generate HDL code. Rather the RT Box firmware has the solver for the circuit implemented on the FPGA. The generated C Code configures and interacts with the static, pre-generated solver on the FPGA.