# How can we include parasitic capacitance in MOSFET?

**URL:** <https://forum.plexim.com/t/how-can-we-include-parasitic-capacitance-in-mosfet/714>\
**Category:** PLECS\
**Tags:** thermal-model\
**Created:** [October 30, 2019, 10:54am UTC](https://forum.plexim.com/t/how-can-we-include-parasitic-capacitance-in-mosfet/714 "2019-10-30T10:54:20Z")\
**Posts on this page:** 2\
**Page:** 1

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**Author:** ![Pallavi](https://avatars.discourse-cdn.com/v4/letter/p/3be4f8/32.png) [@Pallavi](https://forum.plexim.com/u/Pallavi)\
**Post date:** [October 30, 2019, 10:54am UTC](https://forum.plexim.com/t/how-can-we-include-parasitic-capacitance-in-mosfet/714/1 "2019-10-30T10:54:20Z")

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I’m modelling synchronous Buck Converter in discontinuous conduction mode and I want to check the ringing effect caused due to the parasitic capacitance of semiconductor device. But I’m not able to incorporate this in semiconductor model.

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**Author:** ![Kris\_Eberle](https://dub1.discourse-cdn.com/flex006/user_avatar/forum.plexim.com/kris_eberle/32/6_2.png) [@Kris\_Eberle](https://forum.plexim.com/u/Kris_Eberle)\
**Post date:** [November 1, 2019, 8:00pm UTC](https://forum.plexim.com/t/how-can-we-include-parasitic-capacitance-in-mosfet/714/2 "2019-11-01T20:00:37Z")

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The PLECS power semiconductors are based on ideal switch implementations and are therefore not recommended for device/physical modeling applications. You can add a capacitor across the drain and source (Cds), but the gate input is a control/signal input so the Miller capacitances cannot be directly included. It is possible to develop a custom behavioral model yourself, but this is not trivial.