# How to parallel N electrical ports in PLECS Blockset?

**URL:** <https://forum.plexim.com/t/how-to-parallel-n-electrical-ports-in-plecs-blockset/3128>\
**Category:** PLECS\
**Tags:** plecs\
**Created:** [June 1, 2026, 6:11pm UTC](https://forum.plexim.com/t/how-to-parallel-n-electrical-ports-in-plecs-blockset/3128 "2026-06-01T18:11:53Z")\
**Posts on this page:** 2\
**Page:** 1

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**Author:** ![stratoscwq](https://avatars.discourse-cdn.com/v4/letter/s/977dab/32.png) [@stratoscwq](https://forum.plexim.com/u/stratoscwq)\
**Post date:** [June 1, 2026, 6:11pm UTC](https://forum.plexim.com/t/how-to-parallel-n-electrical-ports-in-plecs-blockset/3128/1 "2026-06-01T18:11:53Z")

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In PLECS, I have N identical subcircuits whose outputs I want to connect in parallel, where N is a parameter defined before the simulation starts but may vary between runs. The subcircuits are instantiated as a port array of width N. How can I programmatically parallel-connect these N electrical ports, given that I cannot hardcode the number of branches? Wire Multiplexer doesn’t seem to work here since it requires a fixed, known width at design time.

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**Author:** ![Bryan\_Lieblick](https://dub1.discourse-cdn.com/flex006/user_avatar/forum.plexim.com/bryan_lieblick/32/10_2.png) [@Bryan\_Lieblick](https://forum.plexim.com/u/Bryan_Lieblick)\
**Post date:** [June 2, 2026, 1:13am UTC](https://forum.plexim.com/t/how-to-parallel-n-electrical-ports-in-plecs-blockset/3128/2 "2026-06-02T01:13:50Z")

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Refer to the [Multi-phase Synchronous Buck Converter](https://docs.plexim.com/plecs-demos/power-supplies/multiphase-synchronous-buck-converter/) PLECS Demo Model and the [Implicit Model Vectorization](https://www.plexim.com/support/tutorials) Tutorial.

The key is the [Wire Selector](https://docs.plexim.com/plecs/latest/components-by-category/wireselector/#component-wireselector) component. The screenshot from the Multi-phase Synchronous Buck demo is instructive. The input side (marked with a dot) has a width of 1. The output side has a width of `nPhase` where the value can vary based on the mask / model initialization commands. The input signal branches `nPhase` times to separate parallel circuits. The input width to all the gate signals is `nPhase` and so is the width of the `iph` measurement.

 ![image](https://europe1.discourse-cdn.com/flex006/uploads/plecs/original/2X/8/8158560dd9860e1d1927b432e4961588a53bcd94.png)