# Interleaved Half Bridge block **URL:** \ **Category:** PLECS\ **Tags:** plecs\ **Created:** [July 18, 2025, 6:46pm UTC](https://forum.plexim.com/t/interleaved-half-bridge-block/2348 "2025-07-18T18:46:46Z")\ **Posts on this page:** 2\ **Page:** 1
**Author:** ![ppfon](https://avatars.discourse-cdn.com/v4/letter/p/7ab992/32.png) [@ppfon](https://forum.plexim.com/u/ppfon)\ **Post date:** [July 18, 2025, 6:46pm UTC](https://forum.plexim.com/t/interleaved-half-bridge-block/2348/1 "2025-07-18T18:46:46Z")
Reading the Thierry Meynard’s book on converter vectorized models using PLECS I found this schematic: ![image](https://europe1.discourse-cdn.com/flex006/uploads/plecs/original/2X/0/0619e04f55c8e55458868b9e6e4b3133434e5c64.png) I have no doubts regarding the wire selector blocks and how they’re connected, but i can’t understand how the commutation cell block is built for a generic nP number of branches. PLECS has two blocks to represent vectorized half bridges converters ((b) in the image below), thogh they implement `n’ half bridge cells in series for a single branch. I want to represent ‘n’ half bridge cells in parallel instead. ![image](https://europe1.discourse-cdn.com/flex006/uploads/plecs/original/2X/6/6412584c08ea8aaed169868e1ebd37186f4c0ffa.png) How can I build a vectorized half bridge converter in order to simplify this circuit schematic? ![image](https://europe1.discourse-cdn.com/flex006/uploads/plecs/original/2X/7/7c764b7dc88ad876ed87cf8edc2c5ff266380fbc.png) Thanks! ---
**Author:** ![Kris\_Eberle](https://dub1.discourse-cdn.com/flex006/user_avatar/forum.plexim.com/kris_eberle/32/6_2.png) [@Kris\_Eberle](https://forum.plexim.com/u/Kris_Eberle)\ **Post date:** [July 18, 2025, 7:24pm UTC](https://forum.plexim.com/t/interleaved-half-bridge-block/2348/2 "2025-07-18T19:24:00Z")
Hello, please see our Tutorial #107 on Vectorization in PLECS here: [Tutorials | Plexim](https://www.plexim.com/support/tutorials). Let us know if you are successful with this information.