# Phase shift modulation simulation in dual active bridge converter

**URL:** <https://forum.plexim.com/t/phase-shift-modulation-simulation-in-dual-active-bridge-converter/1782>\
**Category:** PLECS\
**Tags:** dual-active-bridge\
**Created:** [February 13, 2025, 8:59am UTC](https://forum.plexim.com/t/phase-shift-modulation-simulation-in-dual-active-bridge-converter/1782 "2025-02-13T08:59:41Z")\
**Posts on this page:** 1\
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**Author:** ![Bryan\_Lieblick](https://dub1.discourse-cdn.com/flex006/user_avatar/forum.plexim.com/bryan_lieblick/32/10_2.png) [@Bryan\_Lieblick](https://forum.plexim.com/u/Bryan_Lieblick)\
**Post date:** [February 13, 2025, 3:04pm UTC](https://forum.plexim.com/t/phase-shift-modulation-simulation-in-dual-active-bridge-converter/1782/2 "2025-02-13T15:04:02Z")

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First, I’ll note there is a “Variable Phase PWM” block in the PLECS library. The underlying implementation is a C-Script, so it may be more difficult to understand, but the block is better documented than the phase shift PWM in the DAB demo model. The sampling behavior also better aligns with a digital phase-shift controller. See the component help for additional information.

Regarding the model you’re referencing, I would suggest adding additional scopes to analyze the block behavior. Please see the attached model which I used to generate the annotated scope capture below.

[phaseshiftpwm.plecs](https://forum.plexim.com/uploads/short-url/4eWLivcN2RQeUjvPCKmkgQTxP7o.plecs) (26.9 KB)

The block input is between -1 and +1 resulting in a phase shift of -180 or +180 degrees, respectively, between the primary and secondary gate signals. The output signals have a fixed duty cycle of 50%. One can see the “On carrier” and “Off carrier” waveforms are phase shifted 180 degrees from each other. This ensures the duty cycle is set to 50%.

The “Mpri” value (0.5 - m\*0.25) sets the compare for when the primary turn-on and turn-off events happens. The turn-on is when (“On carrier” - “Mpri”) transitions from negative to positive, which generates a hit crossing event in the PLECS Solver. This sets the SR flip-flop for “G\_pri” to a logical true output. The turn-off is when (“Off carrier” - “Mpri”) transitions from negative to positive, resetting the SR flip-flop for “G\_pri” to a logical false output.

The “Msec” value (0.5 + m\*0.25) value sets the behavior for the secondary turn on, which has an identical logic scheme but with a different compare value. Since the primary and secondary have the same carrier waveform, adjusting the compare values of both the primary and secondary results in a phase shift. Centering the compare values to 0.5 makes it easier to have both positive and negative phase shifts.

 ![phaseshiftpwm](https://europe1.discourse-cdn.com/flex006/uploads/plecs/original/2X/3/352b6e80c7d94b0b59c9dfe8e718036d74cd516b.jpeg)

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