# PWM Harmonic Spectrum: Analog and Digital Controllers Compared

**URL:** <https://forum.plexim.com/t/pwm-harmonic-spectrum-analog-and-digital-controllers-compared/2948>\
**Category:** Technical Articles\
**Tags:** plecs, control, pwm, plecs-coder, c2000\
**Created:** [March 27, 2026, 11:54am UTC](https://forum.plexim.com/t/pwm-harmonic-spectrum-analog-and-digital-controllers-compared/2948 "2026-03-27T11:54:57Z")\
**Posts on this page:** 1\
**Page:** 1

<div class="post-metadata">

**Author:** ![Beat\_Arnet](https://dub1.discourse-cdn.com/flex006/user_avatar/forum.plexim.com/beat_arnet/32/9_2.png) [@Beat\_Arnet](https://forum.plexim.com/u/Beat_Arnet)\
**Post date:** [March 27, 2026, 11:54am UTC](https://forum.plexim.com/t/pwm-harmonic-spectrum-analog-and-digital-controllers-compared/2948/1 "2026-03-27T11:54:58Z")

</div>

You have run a frequency sweep, in PLECS or on the bench, and something looks off near Nyquist: the phase hooks upward instead of continuing its descent, or the gain rolls off more steeply than your plant model predicts. Before you conclude your model is wrong, consider this: what looks like an unmodeled pole or zero may in fact be aliasing – an artifact that is inherent to synchronous sampling, not a property of the plant.

This article gives you a precise picture of the PWM harmonic spectrum and explains why an analog and a digital controller see it very differently. With that picture in hand, you can read a Bode plot for what it actually contains.

## Fixed Duty Cycle Spectrum

A PWM signal at switching frequency f\_{sw} and duty cycle D has harmonic amplitudes (normalized to the bus voltage):

|c\_n| = \frac{2}{n\pi}\,|\sin(n\pi D)|, \qquad n \geq 1

The DC component is c\_0 = D. Amplitudes roll off as 1/n, so the switching fundamental always dominates.

The amplitudes are independent of carrier shape [[2]](#ref-2). Trailing-edge, leading-edge, and symmetrical (triangle) carriers all produce the same harmonic magnitudes. Carrier shape affects only the phase of each harmonic, not its amplitude.

A given harmonic is suppressed wherever nD is an integer. At D = 0.5 all even harmonics vanish due to half-wave symmetry; for other duty cycles, the locations of these nulls shift accordingly.

> **Example:** For D = 0.35 and f\_{sw} = 10\text{ kHz}, the fundamental at 10 kHz has amplitude |c\_1| = (2/\pi)|\sin(0.35\pi)| \approx 0.567. Nulls occur at n = 3, 6, \ldots

The figure below shows the time-domain waveform and its spectrum for D = 0.35, f\_{sw} = 10\text{ kHz}.

 ![](https://europe1.discourse-cdn.com/flex006/uploads/plecs/original/2X/e/ec92c5a6477f1ad9a44d4fa1d2678e2f57509609.png)

## Sidebands, Modulated Duty Cycle

In a real converter the duty cycle varies. For a small sinusoidal perturbation of amplitude \hat{d} at frequency f\_m:

D(t) = D\_0 + \hat{d}\cos(2\pi f\_m t), \qquad \hat{d} \ll 1

Sideband pairs appear around every carrier harmonic at frequencies nf\_{sw} \pm f\_m. The mechanism is the same as AM modulation: the signal at f\_m mixes with each carrier harmonic nf\_{sw}, producing sum and difference frequencies on either side.

The table below lists all spectral components at the PWM output. Amplitudes are normalized to the bus voltage.

| Component | Frequency | Natural sampling | Regular sampling (sym.) |
| --- | --- | --- | --- |
| DC | 0 | D\_0 | D\_0 |
| Modulation tone | f\_m | \dfrac{\hat{d}}{2} | \dfrac{\hat{d}}{2}\,\left\lvert\cos\!\left(\pi f\_m \tilde{D} T\_{sw}\right)\right\rvert |
| n-th carrier harmonic | nf\_{sw} | \dfrac{2}{n\pi}\left\lvert\sin(n\pi D\_0)\right\rvert | same |
| n-th sideband pair | nf\_{sw} \pm f\_m | \dfrac{\hat{d}}{2} | \dfrac{\hat{d}}{2}\,\left\lvert\cos\!\left(\pi f\_m \tilde{D} T\_{sw}\right)\right\rvert |

where T\_{sw} = 1/f\_{sw} and \tilde{D} depends on the modulator type (see [PWM Modulator Delay](https://forum.plexim.com/t/pwm-modulator-delay-analysis-verified-by-plecs/2928)):

| Modulator Type | \tilde{D} |
| --- | --- |
| Asymmetrical Trailing-Edge | D |
| Asymmetrical Leading-Edge | 1-D |
| Symmetrical TE-LE | 1-D |
| Symmetrical LE-TE | D |

Sideband amplitudes are independent of harmonic index n. This holds because the analysis linearizes the perturbed switching instant for small \hat{d}, and to first order no n-dependent term survives. Every carrier harmonic carries sidebands of the same amplitude \hat{d}/2.

For regular sampling, the modulation tone and each sideband pair carry an additional phase shift of -\omega\_m T\_{sw}/2 relative to the naturally sampled case. The carrier harmonics and DC component are unaffected.

The figure below shows the spectrum for D\_0 = 0.35, f\_m = 700\text{ Hz}, \hat{d} = 0.05.

 ![](https://europe1.discourse-cdn.com/flex006/uploads/plecs/original/2X/5/5af58ff256520113299153c8e2e6a7ef7f7e2a7c.png)

## Analog Power Converter

In an analog converter the compensator output is a continuous-time signal. It intersects the carrier at its natural crossing points. There is no sampling step.

A voltage-mode buck converter serves as a concrete example. The switch output drives an LC output filter. The output voltage feeds a Type II op-amp compensator.

 ![](https://europe1.discourse-cdn.com/flex006/uploads/plecs/original/2X/f/f0601dca0066d0871f20f8f409c90ac64e05606c.png)

The LC filter is the only attenuator between the PWM output and the feedback node. Well above the corner frequency f\_0 and below any ESR zero, it attenuates at -40\,\text{dB/decade}, which strongly suppresses higher-order sidebands. If the output capacitor’s ESR places a zero below the switching frequency, the rolloff flattens to -20\,\text{dB/decade} above that zero and sideband suppression is reduced accordingly.

The compensator bandwidth is set well below f\_{sw} [[5]](#ref-5)[[6]](#ref-6), so residual harmonics and sidebands at the feedback node cause negligible duty-cycle perturbation. The sideband amplitude reaching the feedback node is:

\left|H\_{LC}(nf\_{sw} \pm f\_m)\right| \cdot \hat{d}/2

The figure below shows the LC filter Bode plot overlaid with the harmonic and sideband frequencies. The first carrier harmonic is attenuated by -33\text{ dB} and the first-harmonic sidebands by -31 to -34\text{ dB}.

 ![](https://europe1.discourse-cdn.com/flex006/uploads/plecs/original/2X/5/5ac1ace459fa8559a6f96ae67ddf7f90a496b837.png)

## Digital Power Converter

In a digital converter the synchronous sampler clocks at f\_{sw}. It acquires one sample per control cycle at a fixed phase relative to the carrier. The switch output spectrum is unchanged: same carrier harmonics at nf\_{sw}, same sideband pairs at nf\_{sw} \pm f\_m. What changes is how the controller observes them.

 ![](https://europe1.discourse-cdn.com/flex006/uploads/plecs/original/2X/9/976b53033b324bfc54d73bb2069c6ae2bd3ccede.png)

### Carrier Harmonics Fold to DC

Any signal component at an exact integer multiple of f\_{sw} has the same value at every sample instant. The sampler sees it as a fixed DC offset. It is invisible to the digital compensator.

For a symmetrical carrier, sampling at the carrier peak or valley is self-anti-aliasing for the inductor current [[1](#ref-1),[3](#ref-3)], but not necessarily for the capacitor voltage, whose ripple is phase-shifted relative to the current. Sensor bandwidth limitations can shift the phase further, so the optimal sample point may differ from the natural overflow or underflow event.

Sampling away from the optimal phase creates a DC error that the compensator cannot distinguish from a genuine regulation error.

 ![](https://europe1.discourse-cdn.com/flex006/uploads/plecs/original/2X/3/3ec8d072b56a997dad6b4690ab9563508a2639fb.png)

In practice the sampling instant is set by hardware, not software. The C2000 PWM block provides two independently configurable trigger outputs: the ADC trigger and the Task trigger. Each can fire at carrier underflow, carrier overflow, or both. A trigger divider reduces the rate by an integer factor while preserving the phase relationship to the carrier.

The compare register shadowing parameter (reload at underflow or overflow) determines when a new duty command takes effect. This fixes the effective modulator delay T\_{eff}. This is the hardware realization of the synchronous sampling and N-cycle modulator analyzed in the article on [PWM modulator delay](https://forum.plexim.com/t/pwm-modulator-delay-analysis-verified-by-plecs/2928).

The choice between underflow and overflow matters. Underflow places the sampling instant at the carrier minimum, the latch point for a symmetrical TE-LE modulator, where the carrier is about to rise toward the duty threshold. Overflow places it at the carrier peak, the latch point for a symmetrical LE-TE modulator. The two choices yield different T\_{eff} values and therefore different alias phase angles \alpha = 2\pi f\_{sw} T\_{eff}, as explained in the next section.

### Sidebands Alias to the Control Frequency

All sideband components at nf\_{sw} \pm f\_m fold back to f\_m [[4]](#ref-4). The dominant contribution is n=1: the sideband at f\_{sw} - f\_m is the closest alias to f\_m, receiving the least attenuation from the plant.

The sampler reports the full aliasing sum at f\_m:

H\_{meas}(f\_m) \;=\; \sum\_{k=-\infty}^{+\infty} G\!\left(f\_m + k\,f\_{sw}\right), \qquad k \in \mathbb{Z}

where G(f) = G\_{PWM}(f) \cdot G\_{plant}(f) is the forward-path transfer function. Each integer k corresponds to one carrier harmonic: k=0 is the direct path at f\_m, k=-1 is the lower sideband at f\_{sw}-f\_m folded back, k=+1 is the upper sideband at f\_m+f\_{sw} folded back.

The plant acts as the anti-alias filter. The n=-1 term lands at f\_{sw}-f\_m, which for typical loop bandwidths receives only moderate attenuation. The n=+1 term lands at f\_{sw}+f\_m, on the far side of f\_{sw}, where the plant attenuation is substantially greater. Terms with |n| \geq 2 are negligible for a converter with a practical output filter, and dropping n=+1 on the same grounds reduces the sum to:

H\_{meas}(f\_m) \;\approx\; G(f\_m) \;+\; e^{\,j\alpha}\,G^\*(f\_{sw}-f\_m)

where \alpha = 2\pi f\_{sw} T\_{eff} is a constant phase set by the effective modulator delay T\_{eff}. The complex conjugate arises because the k=-1 term evaluates G at the negative frequency f\_m - f\_{sw}. For any real-valued system G(-f) = G^\*(f), so G(f\_m - f\_{sw}) = G^\*(f\_{sw} - f\_m).

The alias-to-direct amplitude ratio is a useful parameter:

r(f\_m) = \frac{|G(f\_{sw}-f\_m)|}{|G(f\_m)|}

At low f\_m, the mirror frequency f\_{sw}-f\_m is deep in the plant stopband and r is small. As f\_m approaches f\_{sw}/2 the two frequencies converge and r rises toward unity.

Two examples illustrate how different plants produce qualitatively different distortions for the same modulator.

**LC Plant with an ESR zero well above Nyquist:** The figure below shows r(f\_m) for an LC plant with f\_0 = 1\text{ kHz}, Q = 5, f\_{sw} = 10\text{ kHz}. The filter capacitor is assumed to have very low series resistance, and therefore the zero caused by the ESR is at a high frequency and can be neglected.

 ![](https://europe1.discourse-cdn.com/flex006/uploads/plecs/original/2X/f/fada1ae1e8325b949007d331597ffa059d7ef3f2.png)

The table gives the alias-to-direct ratio at selected frequencies for this example.

| f\_m | Alias at f\_{sw} - f\_m | Atten. at f\_m | Atten. at f\_{sw} - f\_m | Alias / Signal |
| --- | --- | --- | --- | --- |
| 1\text{ kHz}\ (f\_{sw}/10) | 9\text{ kHz} | +14\text{ dB} | -38\text{ dB} | -52\text{ dB} |
| 2\text{ kHz}\ (f\_{sw}/5) | 8\text{ kHz} | -12\text{ dB} | -36\text{ dB} | -24\text{ dB} |
| 3.3\text{ kHz}\ (f\_{sw}/3) | 6.7\text{ kHz} | -21\text{ dB} | -33\text{ dB} | -12\text{ dB} |
| 4\text{ kHz}\ (0.4\,f\_{sw}) | 6\text{ kHz} | -24\text{ dB} | -31\text{ dB} | -7\text{ dB} |
| 4.5\text{ kHz}\ (0.45\,f\_{sw}) | 5.5\text{ kHz} | -26\text{ dB} | -30\text{ dB} | -3\text{ dB} |

Note that for a second-order plant operating well above its corner frequency, the alias-to-direct ratio depends only on the attenuation difference between f\_m and its mirror at f\_{sw} - f\_m. Since both frequencies are in the -40\,\text{dB/decade} rolloff region, that difference is set by their ratio (f\_{sw} - f\_m)/f\_m alone, making the threshold largely independent of the absolute values of f\_0 and f\_{sw}.

Once r is significant, errors appear in both magnitude and phase. Their character depends on the angle of the alias phasor e^{j\alpha}G^\*(f\_{sw}-f\_m) relative to the direct phasor G(f\_m), which in turn depends on \alpha and on the plant’s own phase responses at f\_m and at f\_{sw} - f\_m.

When no zeros fall within the measurement band, both G(f\_m) and G(f\_{sw}-f\_m) are in the -40\,\text{dB/dec} rolloff region near Nyquist, and for a typical \alpha the alias phasor is roughly co-directed with the direct phasor. The vector sum is longer than the direct alone, so the measured magnitude rolls off more slowly than the true plant, and the resultant angle is less negative, producing an upward phase hook near Nyquist. The phasor diagram below illustrates both effects at two frequencies.

 ![](https://europe1.discourse-cdn.com/flex006/uploads/plecs/original/2X/3/3bb71079cb0a8e6b77b419e155ce433ae66f62ee.png)

**LC Plant with an ESR zero below Nyquist:** To illustrate how a plant zero within the measurement band changes the aliasing picture, consider a buck converter with a higher switching frequency of f\_{sw} = 100\,\text{kHz} and a resonant frequency f\_0 = 1.1\,\text{kHz}. The output capacitor has non-negligible ESR, placing a zero at 14.5\,\text{kHz}, well below the Nyquist frequency. The PLECS model below shows the converter parameters.

 ![](https://europe1.discourse-cdn.com/flex006/uploads/plecs/original/2X/9/91878e08350eed9d8d2ccad3891e6251fc9d9b15.png)

This zero changes the picture. It adds phase to both phasors, but the mirror frequency f\_{sw} - f\_m sits further above the zero than f\_m does and therefore accumulates more phase rotation. This swings the alias phasor away from the direct phasor direction. The vector sum is now shorter than the direct term alone, so the measured magnitude falls further than the true plant and the upward phase hook is suppressed.

The figure below overlays three model layers with a frequency response measured directly in PLECS using the Embedded Frequency Response Block: the continuous-time plant G\_{vd}(f), the forward path including the PWM modulator transfer function G\_{PWM}, and the full aliasing sum H\_{meas} as seen by the MCU. The model and simulation agree closely across the full band.

 ![](https://europe1.discourse-cdn.com/flex006/uploads/plecs/original/2X/4/4fea9fe80c3b679665633a78d5aca58d46213137.png)

The PLECS controller schematic used for this simulation is shown below. It uses the Embedded Frequency Response Analysis (EFRA) Block to inject a swept sinusoid at the duty-cycle input and record the resulting output voltage, replicating what a hardware FRA would measure on the physical converter. The ADC is triggered synchronously with the PWM carrier, firing on every second overflow, which gives a sampling frequency f\_s = f\_{sw}/2 = 50\text{ kHz} and sets the Nyquist boundary at 25 kHz.

 ![](https://europe1.discourse-cdn.com/flex006/uploads/plecs/original/2X/9/9e74ae76624c8739a3914746294089582a5591f0.png)

These two examples are not exhaustive. A first-order plant, or any other pole-zero arrangement, will produce its own characteristic distortion. The aliasing sum, however, is always present in any frequency response measured by a synchronously sampled digital controller. The practical implication is to place the crossover frequency well below the region where r(f\_m) becomes significant, so that loop gain and phase margin are not affected by the aliasing distortion.

#### Nyquist Phase: Always a Multiple of 180°

At f\_m = f\_{NYQ} = f\_{sw}/2, the aliasing sum pairs each term k with term -(k+1). The two arguments are complex conjugates of each other, so every pair collapses to twice its real part:

H\_{meas}(f\_{NYQ}) = 2\sum\_{k=0}^{\infty}\operatorname{Re}\!\left\{G\!\left(f\_{NYQ} + k\,f\_{sw}\right)\right\}

This holds for any real-valued plant, it is a hard algebraic constraint, not a modeling artefact. A purely real result means the phase at Nyquist is an integer multiple of 180°. Which multiple you land on depends on the sign of the sum, set by the accumulated phase of the plant and modulator at f\_{NYQ}.

This can be a useful sanity check: the condition applies only to a frequency response measured on the unit circle. If the FRA is mistakenly run in the full continuous-frequency domain, the ZOH sinc rolls off smoothly through Nyquist and the phase will generally not land on a multiple of 180°.

## Summary

The PWM spectrum is the same whether your controller is analog or digital. What differs is how each architecture observes it.

In an analog loop there is no sampling and no aliasing. Whatever harmonic content survives the plant is suppressed by the compensator’s own bandwidth.

In a digital loop, carrier harmonics fold cleanly to DC, a feature you can exploit by placing the sample instant at the carrier peak or valley. Sidebands are less cooperative: they alias back to f\_m and distort the measured frequency response. The alias-to-direct ratio r(f\_m) = |G(f\_{sw} - f\_m)|\,/\,|G(f\_m)| sets the scale of the error. Where r is small the measurement is faithful; where r is significant the measured response reflects both the direct path and its Nyquist mirror, combined in a way that depends on the plant’s pole-zero structure. The specific distortion (gain up or down, phase hook forward or back) is not a universal signature of aliasing but a consequence of the particular plant being measured. Keep the crossover frequency well below the region where r becomes significant, and any discrepancy near Nyquist is expected and not a modeling error.

## References

[1] L. Corradini, D. Maksimovic, P. Mattavelli, R. Zane, _Digital Control of High-Frequency Switched-Mode Power Converters_, IEEE Press, 2015.

[2] S. R. Bowes and B. M. Bird, “Novel approach to the analysis and synthesis of modulation processes in power convertors,” _IEE Proc._, vol. 122, no. 5, pp. 507–513, 1975.

[3] D. M. Van de Sype, K. De Gussemé, A. P. Van den Bossche, and J. A. A. Melkebeek, “Small-signal Laplace-domain analysis of uniformly-sampled pulse-width modulators,” in _Proc. IEEE PESC_, 2004, pp. 4292–4298.

[4] D. M. Van de Sype, K. De Gussemé, F. M. L. L. De Belie, A. Van den Bossche, and J. A. A. Melkebeek, “Small-signal z-domain analysis of digitally controlled converters,” _IEEE Trans. Power Electron._, vol. 21, no. 2, pp. 470–478, Mar. 2006.

[5] R. D. Middlebrook, “Predicting modulator phase lag in PWM converter feedback loops,” in _Proc. Powercon 8_, Paper H-4, 1981.

[6] C. Basso, _An Intuitive Guide to Compensating Switching Power Supplies_, Stairway Press, 2024.