# Question about nanostep

**URL:** <https://forum.plexim.com/t/question-about-nanostep/1899>\
**Category:** RT Box\
**Tags:** plecs, rt-box\
**Created:** [March 13, 2025, 7:54am UTC](https://forum.plexim.com/t/question-about-nanostep/1899 "2025-03-13T07:54:22Z")\
**Posts on this page:** 2\
**Page:** 1

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**Author:** ![PLLLLL](https://avatars.discourse-cdn.com/v4/letter/p/bcef8e/32.png) [@PLLLLL](https://forum.plexim.com/u/PLLLLL)\
**Post date:** [March 13, 2025, 7:54am UTC](https://forum.plexim.com/t/question-about-nanostep/1899/1 "2025-03-13T07:54:22Z")

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I modified the **On-Board Charger** example to use **nanostep** and successfully ran the simulation.  
However, after connecting the **RT-Box with TI** , even when toggling **PFC and DAB ON** , they do not function properly.

To resolve this, I **attempted to separate the Battery Task to run on the CPU** , but encountered an error (see the attached image).

The error message indicates a conflict between the **Battery Task and DAB Task**.  
How can I properly separate the cores to ensure that nanostep functions correctly?

I would really appreciate any help. Thank you in advance!

 ![Before](https://europe1.discourse-cdn.com/flex006/uploads/plecs/original/2X/c/cb91cb99e42f36b3fb8e85c461dd0386f325dffc.jpeg)  
 ![After](https://europe1.discourse-cdn.com/flex006/uploads/plecs/original/2X/6/6228a7ddfbd663b84ac373692bfb271130f3142b.jpeg)

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**Author:** ![Bryan\_Lieblick](https://dub1.discourse-cdn.com/flex006/user_avatar/forum.plexim.com/bryan_lieblick/32/10_2.png) [@Bryan\_Lieblick](https://forum.plexim.com/u/Bryan_Lieblick)\
**Post date:** [March 13, 2025, 4:47pm UTC](https://forum.plexim.com/t/question-about-nanostep/1899/2 "2025-03-13T16:47:25Z")

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The TI C2000 and STM demo models are being reworked to highlight the latest RT Box features like the Nanostep solver. I’ll send you a version of these models through a direct message. I don’t want an out-of-date version lingering on the forum once there is a public release.

You can actually run the whole circuit on the FPGA, with the PFC stage either as a sub-cycle average or Nanostep configuration. You don’t need CPU multitasking and there’s a smaller time step compared to the CPU based implementation.

Regarding the error message - it’s not particularly clear what error you’re receiving or why without a model. I’ll note that you can only have one instance of the FlexArray solver (i.e. only one Electrical Model Settings block configured for the FPGA) per RT Box.