Hello Oliver,
Thank you for your answer and sorry for my late response (holiday) but I still don’t fully agree.
I will try to explain my problem a little bit better, lets assume I remove these capacitors (in my schematic that I added these are C2…C5). Also lets say that the current through L1 is positive (towards the current source). Switch FET1 is enabled and the current is rising, at some point the switch is going to turn-off. The switch-node voltage is clamped to +Vdc and automatically the diode D2 is going to commutate since the current through the inductor wants to keep running.
With the real converter, the slewrate of the switch-node voltage is limited and will not chance instantaneously. Therefor the voltage across FET1 is approximately equal to 0V and there are no turn-off losses. But since in PLECS the switch-node voltage changes infinitely fast to -Vdc (there is nothing that limits the slewrate such as the capacitors), the simulator thinks the full DC-link voltage is across FET1 and will give turn-off losses for FET1. Although that I already specified in my lookup-table that the turn-off losses are 0J for voltages at 0V.
This I also show in the image that is attached. The current through L1 is positive (see plot 3). The switch-node voltage is at +Vdc and at some point the gate of the highside FET turns-off. The V_SN goes to 0 immediately and thus giving the full DC-Link voltage across FET1 what would normally be 0V since the slewrate of V_SN is limited by the drain-source capacitances and other ones.
Do you understand the problem now that I am encountering?
I have also added an image of the thermal losses lookup tables for your idea.
