# \#fpga

**URL:** https://forum.plexim.com/tag/fpga/358.md

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## [Modeling discrepancy for induction machine depending on the solver type (FPGA vs. CPU)](https://forum.plexim.com/t/modeling-discrepancy-for-induction-machine-depending-on-the-solver-type-fpga-vs-cpu/3312)

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**Author:** [@Jaeyeon.Park](https://forum.plexim.com/u/Jaeyeon.Park)\
**Replies:** 2\
**Last updated:** [September 16, 2026, 10:05am UTC](https://forum.plexim.com/t/modeling-discrepancy-for-induction-machine-depending-on-the-solver-type-fpga-vs-cpu/3312 "2026-09-16T10:05:39Z")

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Test environment PLECS 5.0.4 and 4.9.9 are tested. (standalone) RTBOX3 with firmware 4.0.7 and 3.1.8 are tested. Dear Plexim My name is Jaeyeon Park, and I am a Ph.D. student at Seoul National University, South Korea…

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## [Simulating Verilog Logic in PLECS via Verilator](https://forum.plexim.com/t/simulating-verilog-logic-in-plecs-via-verilator/3238)

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**Author:** [@Munadir\_Ahmed](https://forum.plexim.com/u/Munadir_Ahmed)\
**Replies:** 0\
**Last updated:** [July 23, 2026, 8:18pm UTC](https://forum.plexim.com/t/simulating-verilog-logic-in-plecs-via-verilator/3238 "2026-07-23T20:18:24Z")

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Introduction If your control logic is written in Verilog, headed for an FPGA or ASIC down the line, you’ll eventually want to validate it in PLECS. PLECS can’t run Verilog directly, so the usual options are to hand-trans…

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## [Genrating code for FPGA simulation](https://forum.plexim.com/t/genrating-code-for-fpga-simulation/1333)

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**Author:** [@Shridhara\_Gangaraju](https://forum.plexim.com/u/Shridhara_Gangaraju)\
**Replies:** 3\
**Last updated:** [March 21, 2024, 11:16am UTC](https://forum.plexim.com/t/genrating-code-for-fpga-simulation/1333 "2024-03-21T11:16:03Z")

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I am trying to generate code for FPGA simulation. As mentioned in “help”, I’m currently using minimal\_example\_demo -\> boost model to generate code for FPGA simulation. I wanted to see how PLECS Coder generates code for F…

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## [Is there any way to program the FPGA inside RT-box3 directly?](https://forum.plexim.com/t/is-there-any-way-to-program-the-fpga-inside-rt-box3-directly/1278)

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**Author:** [@Battur\_Batkhishig](https://forum.plexim.com/u/Battur_Batkhishig)\
**Replies:** 2\
**Last updated:** [October 24, 2023, 12:07pm UTC](https://forum.plexim.com/t/is-there-any-way-to-program-the-fpga-inside-rt-box3-directly/1278 "2023-10-24T12:07:22Z")

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## [Hi, how do I adjust the FPGA prescaler for the variable PWM block?](https://forum.plexim.com/t/hi-how-do-i-adjust-the-fpga-prescaler-for-the-variable-pwm-block/1277)

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**Author:** [@Battur\_Batkhishig](https://forum.plexim.com/u/Battur_Batkhishig)\
**Replies:** 2\
**Last updated:** [October 11, 2023, 6:14pm UTC](https://forum.plexim.com/t/hi-how-do-i-adjust-the-fpga-prescaler-for-the-variable-pwm-block/1277 "2023-10-11T18:14:19Z")

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## [Interfacing Xilinx Zedboard or Kintex 7 (FPGA) with PLECS RT Box for HIL test](https://forum.plexim.com/t/interfacing-xilinx-zedboard-or-kintex-7-fpga-with-plecs-rt-box-for-hil-test/670)

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**Author:** [@satheesh21](https://forum.plexim.com/u/satheesh21)\
**Replies:** 1\
**Last updated:** [July 2, 2019, 2:27pm UTC](https://forum.plexim.com/t/interfacing-xilinx-zedboard-or-kintex-7-fpga-with-plecs-rt-box-for-hil-test/670 "2019-07-02T14:27:49Z")

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Hello, I would like to interface SOC FPGA(Xilinx Zedboard) or Kintex 7(FPGA) with PLECS RT box. I know that RT box supports TI Launchpad interface board but I would like to know is there any interface board for interfac…