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Help needed with full H-Bridge design for switching power loss calculation

+1 vote

Hello, I’m having trouble finding good numbers to use for my switching power losses in a FET in a full H-Bridge design. I have the conduction losses for the high side, RR losses and body diode conduction losses for the low side rectifier, but the switching losses ( different main power switching losses please see on the high side (however minimal in my application) just will not come to me. 

I will attach below a page from a book that I use as my baseline equation and the corresponding waveform. The formula is Psw = (1/2) Vin * Io * (tc,on + tc,off) * fc, where Vin is my power supply/drain-source voltage, Io is the average current through the load (when FET is fully on), and fc is the switching frequency. Getting tc,on and tc,off from the datasheet using a combination of gate charge, gate resistance, and FET driving voltage and current is my problem. 

From the looks of this equation and waveform, tc,on is defined from when the current through the drain starts to rise to the point when the drain to source voltage is only Rds*Io, and tc,off is defined from when the drain to source voltage starts to rise until the drain current ceases. 

I’ve looked at several datasheets of various FETs for indications of these time values, and the result to me is very ambiguous. Let’s take for example the .

It gives 6 different times under its switching characteristics, however they are not specific for my load current, gate resistance, power supply voltage and gate voltage (and none of them seem to give me a clear value for tc,on and tc,off anyway). 

So I guess my clear-cut questions is this: How do I find these switching times given the values (such as gate charge, Vgs(th)) and the characteristic curves on a FET’s datasheet? 

Thank you very much for any assistance.

asked Feb 23 by Joshua_S (13 points)

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