I would like to investigate different modulation strategies for a 3-LVL-ANPC-SiC topology under different operating points in terms of overall efficiency and power dissipation (temperature) per switch.
To additionally investigate any overvoltages occurring at the switches, I would like to implement the parasitic drain source capacitances (C_DS = C_oss - C_rss). (Coss, Crss from the data sheet specifications)
I had already asked a question here regarding the occurrence and non-solving of algebraic loops at some operating points.
If I now install a drain source capacitance in parallel to the body diode as shown in the attached picture, I always get the following error message, regardless of the operating point under consideration:
Could not solve the algebraic loop comprising the following components:
This leads to an immediate termination of the simulation, even at the operating points that previously worked without the additional capacity.
Hence my question: Is there a way to add an additional drain source capacitance for each switch without aborting the simulation due to not solving an algebraic loop?
I would really appreciate an answer. I have attached pictures to illustrate the problem.