Genrating code for FPGA simulation

Question

I am trying to generate code for FPGA simulation. As mentioned in "help", I'm currently using minimal_example_demo -> boost model to generate code for FPGA simulation. I wanted to see how PLECS Coder generates code for FPGA simulation so I followed these steps:

1. Configured Electrical Model Settings on schematic to FPGA

2. Set Target on Coder window to RTBox 3.

3. Clicked on build to generated code

However, Coder still generates C code where as for FPGA implementation, we need HDL code. I'm finding it hard to understand how FPGA simulation works with C code. or am I missing something in this major update?

Note: I'm using PLECS 4.8.1 with TSP 3.0.1

Answer 1

Shridhara, that is the correct workflow to program the RT Box with the electrical model simulated on the FPGA.  When you actually program the RT Box you will see the FPGA step size appear in the RT Box's physical display as well as in the RT Box web interface.

Regarding the generated code, the PLECS Coder does not generate HDL code.  Rather the RT Box firmware has the solver for the circuit implemented on the FPGA.  The generated C Code configures and interacts with the static, pre-generated solver on the FPGA.

Comments

Hi Bryan, thank you for replying!

Do you mind elaborating more on the pre-generated solver please?

Thank you!

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The solver is Plexim's closed-source IP for electric circuit simulation and is not available to the user.