Is there a way to model the parasitic capacitances between gate-drain and gate-source of a mosfet? As the gate is a signal input I tried to use a controlled voltage source which is turned on simultaneously with the gate. The gate-drain and gate-source capacitances are actually nonlinear and depend on the drain-source voltage. Is this possible to model with the variable capacitor or will the algebraic loop increase the computation time much?
Theoretically you can build a behavioral switch model using various primitives, but I’m not sure how well it correlates to the physical switch, this is quite some work, and it is certainly not the intention of PLECS. If this is something that you hold serious interest in though, please email your inquiry to support@plexim.com and we can discuss it in more detail.