Noise in frequency response plot

General
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1

I am trying to get bode plot of LLC converter using Frequency Response tool. But the plot has a lot of noise. Can you please help me understand what is happening?

Bode_Plot.plecs (256.4 KB)

2

Hi Praneeth,

I would highly recommend not using the Impulse Response measurement to generate the Bode plot for an LLC converter. Additionally, Multitone Analysis may not be the best approach either. Instead, I highly recommend using the new Frequency Response tool introduced in PLECS 5.0.

Please see the following documentation for details:

I also noticed that the perturbation amplitude in your simulation is quite large. Since your control parameter is the normalized frequency (fn), an amplitude of 0.1 results in a 10% deviation of the control signal. This is likely causing a large-signal disturbance rather than a small perturbation around the operating point.

I configured the newly added Frequency Response tool in the attached model and also limited the measurement to frequencies below the Nyquist frequency.

Bode_Plot_MAEdits.plecs (250.2 KB)

I get the following result:

image
image3000×3000 412 KB

You will likely need to adjust the perturbation amplitude and number of frequency points to obtain smoother curves. However, this is somewhat difficult to do with your current model because of how the MCU is modeled.

The way the ePWM peripheral is currently modeled is quite computationally inefficient, and I would not recommend this modeling approach. It makes investigating the behavior of the model much more difficult.

I’m also curious why you are simulating the 100 MHz system clock. You could simplify the model considerably by using the PLECS TI peripheral models, which have an efficient implementation of the ePWM module. This would allow you to simulate and investigate the same ePWM configuration without requiring the simulation to run at a sub-nanosecond time step.

Hope this helps!

3

Hi Munadir,

Thank you for an excellent response.

Initially I was trying C2000 peripherals in PLECS, but I could not find all the features of C2000 device peripheral. So I resorted to emulating the peripheral myself.

And in my application, I will do SFRA( which generates bode plot of the system using C2000 device). So I want to to match the plot in simulation with the plot from SFRA.

I used 6.25ns in C scripts because this is the time period of the c2000 device I am using. I want to see the EPWM counter, ramp generator of CMPSS discretized with this clock frequency.

Thanks again,

Praneeth

4

Hi Praneeth,

I would be very interested in understanding which features or limitations you encountered so that we can relay that information to the development team. This would be useful for roadmap planning, so any additional insight you can provide would be greatly appreciated.

We may have an experimental block that could be useful for this. I will message you directly in case you are interested.

I would still highly recommend against this approach because most of the simulation steps associated with those clock ticks are unnecessary.

For example, let’s say your CMPx value is 500 and PRD is 999, and you set the PWM high when the counter reaches 0 and turn it off when the counter reaches CMPx. The simulation only needs to take steps at the points where something changes, such as counter = 0 and counter = 500, and potentially counter = 999 depending on the configuration. All of the other simulation steps for the counter do not affect the PWM output state and therefore do not provide useful information to the simulation.

You are certainly welcome to implement the modulator in whatever way best suits your application, but using a 6.25 ns simulation step will make the simulation significantly slower and can make debugging and investigating your model much more challenging.

5

Yes please. I would be very much interested to know details about how you implement SFRA.

And I will list out the features which I could not find with Plecs C2000 periherals.

Thanks

Praneeth