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Welcome to PLECS User Forum! :wave:
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0
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1352
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July 4, 2024
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About the General category
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231
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July 4, 2024
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Droop control Problem Simulation
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0
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28
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August 12, 2026
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Positive Negative sequence seperation with DDSRF
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1
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26
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August 10, 2026
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How to Generate the Optimal Inner and Outer Phase Shifts for Extended Phase Shift Modulation in a Series Partial-Power Dual Active Bridge Converter?
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0
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37
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August 5, 2026
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Upgrading student licence to a newer version
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1
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30
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August 3, 2026
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Assistance with adapting DAB for RTBox HIL
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10
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120
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July 31, 2026
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Inquiry Regarding Hardware-in-the-Loop (HIL) Simulation Issues
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3
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57
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July 28, 2026
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Why is my conduction loss so low—only 0.9 W?
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1
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40
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July 23, 2026
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I want to add a carrier delay in SVPWM in PLECS demo named three phase voltage source inverter
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3
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45
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July 20, 2026
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Update software to newest version 5.0 , but have some trouble
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3
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77
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July 18, 2026
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Spike Pulses in Variable Phase PWM block
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2
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37
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July 17, 2026
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How to implement a phase-continuous grid frequency step in PLECS?
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1
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31
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July 16, 2026
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Current and Voltage control
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6
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128
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July 14, 2026
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Pv mppt ti c2000
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3
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74
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July 8, 2026
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Non-sampled zero crossings error in Normal mode but not Codegen mode (fixed-step)
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1
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59
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June 23, 2026
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High current stress across all the components in a DAB converter
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2
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71
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June 17, 2026
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Sample time error
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1
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43
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June 12, 2026
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Inconsistency between the original waveform and the waveform after Analog Input
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5
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85
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June 9, 2026
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Malfunction of a rectifier using a transformer
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2
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64
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May 31, 2026
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Code generation error
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3
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77
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May 29, 2026
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Generation of Phase-Shifted Carrier PWM Signals
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6
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219
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May 28, 2026
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Feature Request: Add a tool to export a PLECS schematic to an LLM-readable functional netlist
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1
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129
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May 18, 2026
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Converter Classification
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1
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66
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May 12, 2026
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PLECS student licence on laptop and desktop
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1
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55
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May 11, 2026
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Scope and current bias online RT-Box
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6
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99
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May 5, 2026
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Pulse Delay vs. Discrete-Time Delay for One-Sample Control Delay in Triggered Subsystem
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1
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71
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May 1, 2026
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CRM mode Totem-Pole PFC Test
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1
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69
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April 21, 2026
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Shoot-through in full-bridge inverter with RT Box and TI C2000 when using Switch block
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1
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66
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April 20, 2026
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Signal mismatch between RT Box Analog Out and DSP ADC in external mode
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2
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79
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April 20, 2026
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