Dear All,
I am working with TI C2000 target to produce the pulses for an MMC. The frequency carrier for the PWM is 20kHz, and the frequency for the sinusoidal wave is 50Hz.
When I work with a System clock frequency of SYSCLK of 180MHz and a Discretization Step Size of 1e-6, the code automatically slows down the frequency of the output signals (instead of 50Hz, it is 25Hz) or stops working.
Things change when I decrease the SYSCLK to 100MHz and increase the step size to 100e-6. However, I am unsure whether I am affecting the carrier frequency of 20kHz.
Is there an equation to calculate the optimum values? Is there any relationship between the values of both SYSCLK and Step Size that I must consider?
Thanks for helping!
With the C2000 TSP one cannot set the step size arbitrarily low. Typically one would expect to see a performance degradation below 5 usec. Typically one would set the step size to the 0.5x, 1x, or an integer multiple of the switching period. In your application that would be 50 usec assuming the controls execute once per period.
There is a relationship between SYSCLK and step size, in that the step size is quantized to periods achievable by the system clock. You can automatically round to he nearest step size by configuring the “Step Size Tolerance” setting in the Coder + Coder options + Target + General menu.
A similar restriction exists for the PWM where only certain PWM frequencies are achievable given the quantization of the SYSCLK. The PLECS Coder will warn you if the frequency is not achievable. The PWM block has a “Frequency Tolerance” parameter in the block configuration to adjust the PWM frequency automatically. Alternatively you can adjust the SYSCLK if you have to hit a target switching frequency with minimal error.
Reducing the SYSCLK from 180 MHz to 100 MHz will reduce the computation throughput of your system and increase the PWM quantization for a given frequency.
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Thank you very much for your answer.