Hello all, I need to understand how PLECS define the thermal network between MOSFET/IGBT and Anti-parallel diode. The following model, I reproduced the devices thermal networks externally as shown in the RHS thermal network. When the thermal chain (representing the Heat sink model) parameters are set to zero, Both Tj curves for the diode and MOSFET measured from the converter devices and the external RHS thermal networks matches. But, once I define external thermal resistance for the heatsink, Tj curves from both sides do not match each other. How is the coupling between the MOSFET and the parallel diode is modelled? and what to modify on the external thermal network to produce the same devices Tj curves?
The heat sink in your model serves as a common thermal node for all connected semiconductors. Its behavior depends on the Thermal Capacitance setting:
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If Thermal Capacitance is nonzero: the heat sink behaves as a passive thermal element, storing and dissipating heat.
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If Thermal Capacitance is zero: it acts as an ideal connection point, directly linking all semiconductors to the connected thermal network (e.g., Thermal Chain1 in your case).
This means the semiconductors are thermally coupled only through the heat sink and not directly to each other—unlike in a Thermal Package Description where internal coupling is explicitly modeled. So, your connection setup is generally correct.
The Core Issue: Foster vs. Cauer Thermal Chains
The thermal chains in your semiconductor models are currently modeled as Foster networks, which are mathematical curve fits valid only when used as-is. They are not meant to be modified or extended afterward. Adding a Cauer network in series with a Foster chain is already incorrect from a physical modeling perspective.
Additionally, PLECS automatically converts any Foster chain into a Cauer chain internally for semiconductor models. This is necessary because the switching losses are modeled using a Dirac impulse approach, which cannot be accurately represented with Foster networks.
As a result, you are unintentionally comparing two different implementations:
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Left side: Cauer network only
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Right side: Foster + Cauer network
Recommended Steps to Correct the Model
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Open the Thermal Library and locate the semiconductor components you are using.
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Go to the Thermal Chain tab.
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If the Fix Coefficients button is available, click it to correct any poorly conditioned Foster chain fits.
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Click Convert to Cauer.
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The semiconductor’s thermal chain is now properly converted to a Cauer network with improved quality.
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Use these new Cauer parameters in your thermal network.
After performing these steps, the model should behave consistently. If you still observe discrepancies, please share your PLECS model and thermal description files so I can take a closer look.