Alberto, thanks for following up with my colleague Kris. Please take a look at the attached model, which gives an identical result between the diode and thyristor implementation (apart from thyristor startup). The 3ph diode/thryistor component is setup as a configurable subsystem so you can benchmark the two results easily in the same model.
When using the PLL block, it's important to understand the phase alignment / 0 degree convention from the PLL. The transformation used in the PLL from PLECS results in the 0 degrees position aligning with the peak of the phase A voltage (cos(phi) behavior). I assume in your reference the 0 degree position is aligned with the positive zero crossing (sin(phi) behavior). Take a look at the "Phase Alignment" scope. That would explain the 90 degree phase shift in current from what you would expect.
Another minor adjustment one could make in this model is to place the PLL on the primary Y winding opposed to the secondaries. In this simple model there's less voltage harmonics on the primary which can influence the PLL performance. The delta winding phase is calculated by phase shifting the PLL angle of the primary.
