C2000 Powerstage Protection long delay by turning off

General
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1

Hi there,
I am currently working on a PLECS model and try to generate code to run on a C2000 DSP (TMS320F28379, 2xCPU). In PLECS model we use Powerstage Protection block to stop PWM outputs during overcurrent. The Signal output was connected to a digital output port, which is used to control a LED on hardware board.

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During hardware testing, we observed a significant delay—about 40 ms—between the moment the PWM stops and the corresponding change in the protection signal output:

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Blue: digital output pin LED1, remains at ~2V throughout the scope range. Status jump of LED1 was not visible on the scope.
Yellow: voltage over transistor being controlled by PWM

As stated in help document, there is only delay of 100ms while activating the Powerstage Protection, not by turing off PWM.

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Does anyone have ideas, where this delay could come from?

p.s. the affected CPU has a sample frequency of 25kHz. Block parameters:

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Thanks in advance!

2

The Powerstage Protection block has a dedicated enable GPIO specified in the component mask. Set the “Powerstage enable signal” to “Digital output” and configure the polarity and GPIO number. This GPIO is directly linked to the PWM peripheral status.

When you take the Powerstage Protection block’s signal output and connect it to another Digital Output you are inserting a delay of one sample period. In your case the sample period is 40 usec (1/25e3) so the delay you are observing matches. The Powerstage Protection block’s signal output can be useful for other things such as resetting integrators in your control loop.

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3

Hi Bryan,
thanks for your reply.
Acctually the observed delay was 40 milli seconds, exactly 1000x of the CPU sample period. Such a lang period has made me confused.
And if I use the dedicated DIO pin, in which type the pin be then configured? Push pull or open drain?
BR
Z.W.

4

Acctually the observed delay was 40 milli seconds, exactly 1000x of the CPU sample period. Such a lang period has made me confused.

My apologies for misreading that. Interesting - do you have a model or minimal example you could share? Are you stopping the PWM by changing the “En” input to the powerstage block or are you activating the fault with a Trip Signal input?

And if I use the dedicated DIO pin, in which type the pin be then configured? Push pull or open drain?

It will be push-pull