Problems with application of ePWM block in Digital Control

Coder TI C2000
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1

Hello everyone,

In my past simulation-evaluation exercises using the PLECS Coder 1.10.5 version with PLECS Standalone 4.9.4 I had implemented a discrete PI controller in a single-loop to control the current, also because I developed a cascade controller with the outer loop of voltage on continuous time domain as

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I already discretized the inner-loop by the tustin method (using the same results I had) with sample time Ts=1e-05 seconds, then I applied the discretization of the integral action and employed the discrete delay block for my “artificial delay” h fixed in h=5e-03 seconds, which is a multiple of the sample time, and divided by it corresponds to a Delay Order of 500. The thing is that I have this error on my simulation (using the C2000 blocks)

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But I made the same simulation without the C2000 blocks and I have these nice results

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This is the first time I’m dealing with this error, so if you have any suggestions to solve it, I would appreciate it.

I attached the files 10_Controlled_PIR-PI_Case2 for the simulation without the C2000 blocks and 11_C2000_Controlled_PIR-PI_Case2 for the crash simulation (taking into account there are other signal references since I’m using a current sensor, already validated).

Thanks in advance for your comments!
Erick.
10_Controlled_PIR-PI_Case2.plecs (73.1 KB)
11_C2000_Controlled_PIR-PI_Case2.plecs (123.8 KB)

2

Hello,

This is indicating that the block needs the base sample time (Ts) to be 5e-6 so that all sample times involved are a multiple of the base sample time. The PWM block requires this base sample time being double the frequency to make all appropriate updates properly. Setting your sample time to 5e-6 (or 1/(fsw*2)) solves the issue on my end.

Let us know if you have further questions!

1 Like
3

Thanks for your answer sullivan. My new question is, what is the minimum sample time that PLECS supports? Because I had to set fsw=50e3 to be a sample time of 10e-6 to build my project physically on the launchpad

4

For programming for TI microcontrollers, 5e-6 is the minimum base step size that we support. Anything below this and our task scheduler becomes unable to run. Even at 5e-6 step size, only the most basic of models can be run. Generally we recommend keeping the step size to at least 1e-5 if possible for programming.

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Sample time for task 0 on CPU 0 too small - raise sample time or system clock rate
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Thanks Sullivan, it would be great for the next software updates to reduce the step size, I’m super satisfied with PLECS and C2000 programming.

Greetings!

6

That means we cannot use a 500 kHz sawtooth wave inside of the circuit for comparing or something, as it needs a very low sample time?

7

Effectively yes, if the purpose of the wave is internal to the circuit to use for logic, the step size will never be able to keep up with that wave. You can output a PWM at 500 kHz, but internally the logic cannot run that fast.

8

Hi sahdev, could you describe in a bit more detail what you’re trying to accomplish? There may be an alternative approach that would provide a more efficient solution.