Hi!
CPL_error.plecs (81.8 KB)
I am trying to model a constant power load in PLECS, see figure and document attached. The load is set as a controlled current source, where the current for phase a is determined by:
i_{L,a}=\frac{P^*_L \cdot v_{Load,a}}{v_{Load,a}^2+v_{Load,b}^2+v_{Load,c}^2}
Where $v_{load
}$ is the measured voltage.
I am experiencing some issues with algebraic loops (which I avoid by using a transport delay of 1e-5 seconds to the voltage measurement in the load control, equal to the time step), and mainly, that when I run the circuit, I do not get a sinusoidal voltage nor current in the load.
Could you help me designing this constant power load?
Thank you
