When running a PLECS model in the RT Box, an error occurred. After building the plant, the PLECS software reported a series of errors. After correcting the errors as indicated, the RT Box then displayed a half-bridge short-circuit error message. Despite multiple adjustments to the dead-time and simulation step size, the half-bridge short-circuit error persisted.
I could not recreate your issue and needed to create several modifications to get things to build on my side. These changes might have influenced the ability to recreate the issue.
However, I suspect that there is an actual shoot-through event. Using the TI C2000 PWM you only guarantee that the two switches associated with the ePWMx unit are complementary, but not across multiple PWM units. For example ePWM1 generates sa1 and sa3 while ePWM2 generates sa2 and sa4. However, there’s no ePWM-based guarantee that both sa1 and sa4 (ePWM1A and ePWM2A) cannot both be high at the same time - it depends on the duty cycle inputs. Typically this would be a case where after several minutes of running you would get this issue to some rounding.
How about you improve your model to state where I can out-of-the-box recreate your issue and I can give you debugging tips. Are you using an older version of PLECS or the TI C2000 / RT Box firmware? If so please upgrade to the latest versions as well.
Here are the changes required to even build your circuit:
The Y connected capacitors were miss connected. Two of the capacitors connected to the same (middle) phase.
The Nanostep solver requires a direct connection to a capacitor or voltage source. I removed the series resistances from the AC and DC-side capacitors.
A few obvious issues:
Your PLL never locks, even in offline simulation. If you look at the input to your integrator input (pll frequency) it oscillates wildly, as does your angle. This causes pretty much all measurements to be wrong. You should retune this. You might still see some oscillations due to resonances in the LCL filter unless addressed.
When using the integrator blocks for code generation (specifically the one in your PLL). you should use integrator wrapping and limits where applicable. For example, the integrator you’re using as a clock generator will lose precision as the floating point number grows large. Set it to wrapping instead of post-processing with the MOD function.
Your PI controllers will saturate at the prescribed limits, but they will not have any anti-windup as the anti-windup method is set to “none”. Probably not an issue in testing, but will be a practical problem.
You are using the wrong GPIO for external mode for your C2000 device - for the 28379D control card you should use GPIO [28,29] instead of the default (this is noted in the “External mode GPIO pins” section of the C2000 target support documentation). Actually connecting to external mode will cause your controller to overrun. You can refer to this article for more tips on how to resolve that.