I have a phase shift modulation scheme designed in PLECS standalone. I am using this model in simulink controller for getting switching signals using PLECS blockset. Weird thing is one of the SR flip-flop in the modulation scheme is giving wrong output. Example, when the inputs are 0 1, it gives 0 when ideally it should give 1. SR flip flop2 at the bottom is generating wrong signals. I don’t understand how this is happening. Can anyone suggest something?
Please post your model for further support.