How to Generate a New Pulse When Frequency Changes

General
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1

Dear all,

How can I generate a new pulse when frequency changes? Given the fact that the transition of the switching frequency for a PWM completes only in less than 1 ns (in simulation it is almost a vertical straight line changing from 1 frequency value to another value), how can I detect a frequency change and then generate a new pulse (with duty cycle 50%, starting at rising edge) and repeat until next frequency change hits?

An example switching frequency and the pulse generator I am using are shown in the following figures:

fsw
fsw1920Ă—1920 136 KB

image
image121Ă—135 5.03 KB

Instead of using a rectangular pulse generated at the beginning of simulation or a delayed block, I need to produce a completely new pulse when detecting a frequency change (we don’t know when the frequency will change).

image
image682Ă—536 31.1 KB

(Fig. Testing system)

GenerateANewClockBasedOnFSW.plecs (44.4 KB)

Thank you!

Sincerely,
Mark Lin

2

Mark - have you considered the Variable Frequency PWM block in the PLECS library?

3

Hi Bryan! Yes, I have tried the latest version of Variable Frequency PWM block in the PLECS library. However, it doesn’t work when I have multiple bridge-legs interleaved together with variable frequency. Especially during the frequency transitions, I always get the asymmetric current spikes.

4

Thanks for the update Mark. It’s hard to envision exactly what you’re looking for without further details such as a drawing of exactly you envision the synchronization between the PWM for various channels.

I can make a few genera recommendations:

  • You can peruse the forum for other posts about variable frequency ramp generation, such that you can directly control your carrier. Some examples include post1 and post2.
  • You can also use the TI C2000 block which has some more advanced features for offline simulation. See this post,
5

Thank you for the information Bryan! We are looking for a perfect synchronization between different PWMs without any carrier jumps. As shown in the attached figure, there are noticeable carrier jumps in the second subplot when switching frequency changes, which we believe is the cause of the inductor current spikes.

I will look at the posts you recommend. In the meanwhile, do you have any specific suggestions for us to eliminate the carrier jumps and the corresponding current spikes?

image
image629Ă—629 71.1 KB

(Fig. Clocks, carriers, discrete switching frequency, inductor current for four bridge-legs)

6

Hi Mark, Sorry for the delay while I was traveling. Could you post your model? From your plot it looks like you have both variable phase and variable frequency. The variable frequency actually looks continuous (near 7.03e-3). When there is a step change in phase (near 7.05e-3) it is inherently discontinuous as the new phase is different from the old phase, even if the phase is only changed at certain time intervals (e.g. carrier min/max).

1 Like
7

Hi Bryan, no worries!
Yes, I am using variable phase and variable frequency. Actually, I am using discontinuous switching frequency. Then is there any way to eliminate those carrier jumps when phase changes? I am thinking to make the rising edge of clock signals align with the frequency transitions. That’s why I want to generate a completely new clock signal with a delay. I have attached the simulation files for you. Thanks.

InterleavedOL.m (705 Bytes)
InterleavedOpenLoop.slx (133.4 KB)

8

Mark, A step change in phase will always lead to a carrier jump. You can choose when that jump happens by loading the change in phase immediately, as in your model, or at the zero / period which may reduce the transient.

In your model you are intentionally staggering the phase and then loading the staggered phase immediately. Have you considered updating the phase for all channels synchronous with the carrier min/max of either each channel or a primary carrier? This also gets to the implementation question of how your modulator would actually be constructed.

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9

Hi Bryan, Thanks for your response. Can you describe in more detail how to determine exactly when the carrier jump occurs? For example, you mentioned updating the phase at a zero crossing or at the end of a switching period—could you explain how to implement that in practice, especially in a system with variable switching frequency, variable phase, and 4 bridge legs? Coordinating all of them is quite challenging.

I am staggering the phase because I’m doing interleaving on multiple legs, and I’ve already tried using the first PWM block to provide a primary carrier. Unfortunately, I still see carrier jumps, so the synchronization function of the PWM block doesn’t appear to fix the issue in my setup.

Could you also clarify what you mean by “modulator” in this context? I’d like to understand how the modulator concept is usually applied, so I can get a better handle on managing phase updates or preventing these carrier jumps in my system.