Hello!
I am trying to migrate my current model to a PLECS RT Box demo-style implementation, using the official PLECS MMC RT Box demo as a reference. At the moment, I am still verifying the model in offline simulation.
My goal is to replace the originally built submodule arm, for example the commented-out SM1 module, with the Full Bridges (Series Connected) block, which allows the number of submodules to be configured. I also want to try using PWM Out and PWM Capture instead of my original PSC-PWM generation module, so that the model can later be run on the RT Box.
In the original model, each phase arm has 10 half-bridge submodules. The initial capacitor voltage of each submodule is 5000 V, so the total initial voltage of the arm submodule capacitors is approximately:
10 × 5000 = 50000 V
The original model uses a self-built PSC-PWM scheme. The controller outputs a 10-dimensional reference signal m_vec, which is compared with 10 phase-shifted triangular carriers. The difference then passes through a Relay block to generate 10 channels of 0/1 PWM gate signals.
The original PSC-PWM carrier parameters are approximately as follows:
Carrier frequency: 6000 Hz
Carrier range: 0 to 1
Phase shifts of the 10 submodules: 0, 0.1, ..., 0.9 carrier periods
I have already verified that replacing the original 10 explicit submodules with the Full Bridges (Series Connected) block is feasible. Specifically, I use the full bridge as an equivalent half bridge and only use the +uC/0 states.
The following gate mapping has been tested and works correctly:
Q1 = g_vec;
Q2 = zeros(1, NumCells);
Q3 = 1 - g_vec;
Q4 = ones(1, NumCells);
That is:
g = 1 → Q1 = 1, Q2 = 0, Q3 = 0, Q4 = 1
The submodule is inserted, and the output voltage is approximately 5000 V.
g = 0 → Q1 = 0, Q2 = 0, Q3 = 1, Q4 = 1
The submodule is bypassed, and the output voltage is approximately 0 V.
If I directly use the g_vec generated by the original PSC-PWM plus Relay to drive the new Full Bridges (Series Connected) block, the arm voltage, arm current, and capacitor voltage waveforms are all normal. This indicates that the full-bridge replacement, port connections, gate mapping, capacitor initial values, and voltage measurements are basically not the problem.
The main issue is with replacing the original PSC-PWM by PWM Out/PWM Capture.
I want to change the signal chain from:
m_vec - carrier_vec → Relay → g_vec → Full Bridge
to:
m_vec → PWM Out → PWM Capture → g_vec → Full Bridge
My current PWM Out settings are roughly as follows:
Digital output channel(s): [0:9]
Carrier type: Symmetrical
Carrier frequency: 6000
Carrier limits: [0 1]
Polarity: 1
Turn-on delay: 0
Update: On carrier minimum
Carrier phase shift: I have tried [0:9]/10 and mod([0:9]/10 + 0.25, 1)
When I set PWM Out Update = Immediately, the simulation becomes very slow or appears to hang. Therefore, I mainly tested On carrier minimum, but I am not sure whether this update mode is equivalent to my original continuously compared PSC-PWM implementation.
My current PWM Capture settings are roughly as follows:
Digital input channel(s): [0:9]
Active polarity: 1
Input characteristic: High impedance
Offline behavior: initially tested with Sub-cycle average, later changed to Nanostep
With Sub-cycle average, the output is not a true 0/1 pulse signal. Instead, it represents the high-level duty ratio within one model step, so the waveform takes values between 0 and 1. Therefore, it cannot be directly equivalent to the original Relay output.
After changing the offline behavior to Nanostep, the output of PWM Capture became a 0/1 pulse signal, which is an improvement.
However, even with Nanostep, the 10 PWM signals generated by PWM Out/Capture still cannot reproduce the original PSC-PWM output.
I compared the number of inserted submodules using:
N_old = sum(g_old_vec);
N_new = sum(g_new_vec);
N_err = N_old - N_new;
I found that N_err is not just a small ±1 error occurring around switching edges. Instead, it frequently reaches approximately -10 to +9.
This means that the PWM generated by the current PWM Out/Capture setup differs significantly from the original PSC-PWM in terms of the equivalent arm voltage.
Since each submodule voltage is approximately 5 kV, an insertion-number error of 5 submodules may cause an instantaneous arm voltage error of about 25 kV. Therefore, after connecting this to the full closed-loop model, the arm current and port power become clearly incorrect.
My current understanding is:
The Full Bridges (Series Connected) replacement itself is not the problem.
Driving the Full Bridges (Series Connected) block with the original PSC-PWM also works correctly.
The problem is mainly that PWM Out/Capture cannot reproduce the 10-channel phase-shifted PWM generated by the original PSC-PWM plus Relay.
My questions are:
-
How can I make
PWM OutandPWM Capturein PLECS accurately reproduce the output of my original PSC-PWM plus Relay implementation? -
How should I configure the
Carrier phase shift, theUpdatemode ofPWM Out, and theOffline behaviorofPWM Capture? -
If the final goal is to run the model on the RT Box, is it necessary to force the use of
PWM Out/Capture, or can I keep the original PSC-PWM implementation and run it directly inside the RT Box?
FTDC-box.plecs (487.6 KB)