I am currently working on building my RT Box coder for implementing phase shift modulation in a three-phase dual active bridge design. As part of the process, I need to generate a phase delay of 60° between each signal. Despite trying various approaches within my knowledge, I have not been able to achieve the desired phase delay.
This issue is critical as I am unable to provide the necessary signals to my controller without resolving it. I would greatly appreciate your guidance in troubleshooting and resolving this problem. Your support in helping me figure this out at the earliest would be invaluable.
You have asked the same question in both the Plexim forum and through the support@plexim.com support channel. In the future please ask in only one location as it results in duplicate efforts from our engineering team.
In response to your support ticket where a model was included, my colleague suggested to use a PWM Out (Variable) block from the RT Box Target Support Library. The PWM Out (Variable) block can have a variable phase (and switching frequency) that is controlled by the block inputs. This approach allows PWM generation on the RT Box FPGA which has a significantly smaller clock resolution than is achievable when explicitly modeling carriers using blocks like the Triangular Wave Generator within the simulation.
You should be able to model most modulation schemes using this approach.
