Dear Team,
I am currently working on a Phase-Shifted Full Bridge (PSFB) converter simulation in PLECS Standalone using a peak current mode control technique. In the non–code-generation model, the peak current controller output provides a PWM signal that is used to generate the gate signals for the second leg of the primary-side switches.
For the first leg, the gate signals are produced using a pulse generator with 50% duty cycle. For the second leg, I implemented a T flip-flop where at each falling edge of the peak current controller output toggles the state, providing the required phase shift as in the attached image.
When moving to a TI C2000 code‑generation model, I use the TI Peak Current Controller block and obtain a similar controller output. However, I am unable to reproduce the falling‑edge triggered T flip‑flop logic using the TI target blocks. C‑Scripts are not allowed because they do not compile in the TI Coder workflow.
Could you please advise on the best way to implement this logic for code generation? Specifically:
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How can the falling‑edge detection and T flip‑flop toggling be replicated using TI C2000‑supported blocks?
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Can the TI PWM Variable block be used to implement the required phase-shift behaviour?
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Are there recommended alternatives (e.g., using ePWM modules, CMPSS, or digital compare events) that support this within the code-generation constraints?
Any guidance, example models, or documentation references would be greatly appreciated.
Thank you for your time and support.
Best Regards,
Shamanth
