Dear Plexim Community,
For context: I am have prototyped a low-voltage (48V TO 24V, 2 A) LLC half-bridge converter with GaN switches and synchronous rectification operating at 500 kHz. I have used a PLECS simulation to validate the initial behavior. With initial simulation and hardware validated in open loop, I designed a frequency ramp followed by CC-CV control strategy in PLECS with continuous PI blocks and when that worked, I successfully migrated simulation model from continuous to discrete (even though later I checked here and apparently the Target Support for C2000 discretizes the continuous PI block automatically during Build and Program step).
Now, I have added the necessary C2000 blocks (PWM, ADC, Timer and Control Task Trigger) and kept almost the same control strategy (changed few details to comply with C2000 error messages) but according to the simulation results, the PI block behavior has changed and I do not get the same results as in the first simulations.
Image below shows the initial successful simulation results, in the left side the control variables at zero (reset active) during the frequency ramp (up to 5ms), then the control handover to CC-CV blocks and reasonable waveforms until the output regulates at 25 V around 50 ms in the right side:
In this other image, the failed simulation shows an output voltage slight below 24 V, and completely different curves for the control variables:
Files are attached for reference. I appreciate any help in this topic!
Thank you in advance and best regards,
work_hb_LLC_split_cap_converter all caps - control with f start up for TI C2000.plecs (224.3 KB)
work_hb_LLC_split_cap_converter all caps and control v3 PI blocks and f start up with ESR.plecs (193.1 KB)
Hi,
I have found the 2 errors leading to the issue in the CI2000-compatible version:
- A NOT operator was inverting the “RampDone” signal that should reset (with high level) the integrator at the ramp to CC-CV control handover moment. Now without the NOT block, all control variables are zero during ramp (first image below). This behavior for the reset pin contradicts the documentation description (second image below).
- The C2000 PWM Variable block is not creating phase shift between primary and secondary half-bridges in my C2000-oriented simulation. Even though I feed the ph’ pin of PWM variable block with the output of my current PI block (first image below), the scope that tracks the generated PWMs show them all synced (second image below).
- I did a physical test to validate the PWM generation with phase in another, simpler simulation file (first image below) and achieved corresponding signals from the respective pin in the MCU (second image below).
I do not understand why the PWM has worked in the simpler simulation model and do not work on the full model. I hope someone can help clarify this.
The PLECS models are attached for reference.
work_hb_LLC_split_cap_converter all caps - control with f start up for TI C2000.plecs (222.9 KB)
test500kPWM.plecs (17.1 KB)
Thank you in advance and best regards,
Thanks for sharing the debugging steps you have already undertaken.
This behavior for the reset pin contradicts the documentation description (second image below).
Your screenshot shows the description of the External Reset parameter for the Integrator component, not for the PID component, which includes additional block-specific information: “If level is chosen, the output signal keeps the initial value while the reset input is not 0. Only the integrator in the integral action is reset.”
Note that in your model 1) before the level signal changes the error input to the block is zero and 2) the initial state x0 input is non-zero the entire time.
So if the level input is 1 at the start of the simulation (using NOT gate) the PID output is essentially a feed-forward of the x0 input which is non-zero. Then it transitions to 0 where the integral control is active.
If the level input is 0 at the start of the simulation, then the error signal is 0 and the output is 0 as well. Then the level input goes to 1 and the integrator isn’t active but once again acts as a basic feedforward.
I suspect what you really want is a rising/falling edge based reset and not level.
The C2000 PWM Variable block is not creating phase shift between primary and secondary half-bridges in my C2000-oriented simulation.
You are applying the phase shift to the first channel which is the “primary” channel. You should keep the phase shift of the first channel as 0 and phase shift the secondary channels.
