Dear Plexim community,
I have been struggling with a few questions regarding the usage of PWM (Variable) TI C2000 block and how does it relate to the discretization step.
Ideally, I need to generate a 2x 500 kHz PWM signals, one with phase shift in relation to the other, to drive secondary and primary half bridges of my LLC converter with a phase-shift in order to achieve CC-CV control for charging.
I checked a few different topics before creating this one, but what did not become clear to me is if there is a way (maybe with multi-task approach) to generate a PWM with period (2e-6 s) higher than the discretization step ( 5e-6 s, as far as I checked here and in the documentation).
If not, is this limitation applicable only in the “Run from PLECS Coder” scenario, or if I generate code based on the model with CI2000 blocks and import to CCS software, will this limitation also be imbued into the code import there?
I look forward to any answer that helps me, thanks in advance! Best regards,
There are a few questions in your post:
1. Can the PWM period be decoupled from the model discretizaiton step size?
[Is there a way to] generate a PWM with period (2e-6 s) higher than the discretization step ( 5e-6 s, as far as I checked here and in the documentation).
Yes this is possible. See the “Control Task Execution” section of the TI C2000 TSP User Manual. The control task signal is triggered either by a CPU timer (Timer block) or via a PWM block. Both of these can also be used to trigger an ADC which then triggers the CPU block.
If you want a fixed interrupt rate, then use either the timer block or a fixed-frequency PWM. A variable interrupt rate is also possible when using a variable frequency PWM block, but comes with a several key risks such as resource starvation at high frequencies and the need to adaptively tune controller constants as a function of execution frequency.
I also suggest you review this post discussion the mechanics of changing the trigger interrupt divider and ways to debug controls executing at higher frequencies.
2.What is the is the maximum frequency of the generated PWM signals?
The maximum frequency is not a meaningful metric without knowing the required resolution of the PWM signal. If you need only 1 bit of resolution (only 50% duty cycle) the answer is quite different if you need 10 bits of resolution (1024 different duty cycles achievable). The answer also depends on the system clock frequency which is a function of which MCU you are using and the clocking configuration.
What I can say is that with a variable switching frequency near 500 kHz you will want to enable the high resolution period feature of the C2000 device. This is configured in the “High Resolution” tab of the PWM block. See the attached figure. There also may be limits to how fine-grained of a phase shift you can apply on top of this, but I would need to know more about the application to discuss specifics.
3. Is this behavior influenced by the programming approach
If not, is this limitation applicable only in the “Run from PLECS Coder” scenario, or if I generate code based on the model with CI2000 blocks and import to CCS software, will this limitation also be imbued into the code import there?
This behavior is irrespective of the programming workflow.
