Higher PWM switching frequency in TI auto Code generation

When changing the PWM frequency, you are also changing the amount of time that the generated code has to run (assuming PWM directly/indirectly triggers CPU task and a 1:1 ratio of PWM period to interrupt period, which is default). Going from 10 to >20 kHz results in a change of 100us to <50us to run the code. If the code does not have time to complete within each interrupt then the program execution is halted. You can use the CPU load block to see what the processor load is at 10 kHz and determine the available margin.

You’ll notice in most demo models we have an LED blinking. This LED is a visual indicator that the program is running as expected. If the program terminates then the LED will stop blinking. If the CPU load is marginal, you will notice the MCU code running as expected until external mode is activated, at which point the increase in processor load will halt the execution.

You have a few options. One is to simplify/optimize your model such that requires less computational effort. Applying multi-tasking techniques helps, such that all code does not need to execute in the shortest high priority task. The “Single-Phase PV Inverter” demo model explains the concept well, in addition to the TSP documentation.

Another option is to change the control execution such that you have a PWM period that is an integer divisor of the discretization step size. For example Tdisc=100us (10 kHz) and Tpwm=50us (25 kHz). The control loop will execute at 25 kHz but you can still achieve higher PWM frequencies. This will impact the control bandwidth. If you have the PWM explicitly triggering the ADC, then you will need to set the ADC trigger divider. With 100us/50us the value should be set to 2. A sketch is shown below.

Some additional recommendations are made in this document: https://plexim.com/sites/default/files/tutorials_categorized/rtbox/from_offline_to_realtime.pdf. Items E, F, G, and H are relevant. Having many C-Scripts or State Machine blocks can also be detrimental. You can try these changes out at 10kHz with the CPU load block and see what makes the most impact.

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