Model architecture: Fixed-step Simulink control for code generation combined with variable-step PLECS plant simulation

General
1

I am modelling a half-bridge LLC resonant converter in PLECS, and I want to design a model-based digital controller for TI C2000 code generation. The power electronics of the converter are implemented as a PLECS Circuit inside a MATLAB/Simulink model.

Because the converter is frequency-controlled, I am using the PLECS Variable Frequency PWM block. This block receives a control signal that sets the desired switching frequency.

When I run the system in continuous time (Simulink variable-step, e.g. ode23tb), the simulation works correctly for both fixed and variable switching frequency.

However, when I introduce a time-discrete control algorithm, the simulation fails:

  • The digital controller runs at a fixed sampling period (T_ctrl = 10 µs)

  • The controller output is fed into the PLECS Variable Frequency PWM through a ZOH block

  • The PLECS plant remains simulated with a variable-step solver

  • The simulation then terminates due to too many detected zero crossings

My intended model structure is:

PLECS Plant → ZOH → Fixed-step Simulink Control (C2000 code-gen) → ZOH → PLECS Plant

I looked at the demo model “LLC Resonant Converter with embedded code generation for TI C2000 MCUs”, but in that example the PWM for the C2000 is generated either for an RT Box or the control algorithm is implemented directly inside PLECS.
I want a different architecture: PLECS handles only the power stage, while Simulink (fixed-step) implements the digital controller, and the PLECS plant should continue to run with a variable-step solver.

My questions:

  1. What is the recommended and clean way to make a variable-step PLECS plant and a fixed-step Simulink controller work together, especially when using the Variable Frequency PWM block, which seems to trigger excessive zero-crossing events when driven by a sampled (ZOH) signal?

  2. Are there established modelling patterns or interface strategies to avoid the zero-crossing explosion in this mixed-step architecture?

  3. Which solver is best suited for this type of model?

  4. The issue appears mainly when the frequency control signal changes rapidly, how should this be handled to avoid too many zero crossings?

  5. I get a warning of algebraic loops, is this causing some issues?

2

There are quite a few behaviors and settings that can influence the model behavior, from various solver settings, parameter values, to overall control design. It would be better if you could post your model or a representative example.

3

Hier ist die korrigierte und sprachlich gestraffte Version:

Thanks for the feedback. In the meantime I managed to obtain a more stable simulation, but it still fails in several operating conditions. My goal is to build a clean and reliable simulation architecture that works over the full frequency and load range so that a discrete controller design with code generation becomes feasible.

What I have tried so far: I added relatively high series resistances to all passive components to introduce damping, which improved stability slightly. The real converter uses a half bridge with a split resonant capacitor and primary side clamping diodes. At high load the clamping diodes conduct and the simulation often crashes. For testing, I removed the split resonant capacitor and replaced it with a single series capacitor, but the simulation still becomes unstable when the load R_o is changed. I am currently using the ode15s solver and increased the number of consecutive zero crossings from 1000 to 10000.

My main question is what a clean and robust simulation architecture for this mixed variable step and fixed step setup should look like. A stable plant simulation is essential for the controller design. A simplified model and my current implementation are attached. For now, the model performs frequency steps at different operating points for testing. This model should later be extended with a variant subsystem for discrete controller design. I am using MATLAB 2024a.

Variant_Subsystem.slx (144.2 KB)

Initialize.m (1.5 KB)

4

You can use your variant-based approach and have a discrete system modeled using the approach outlined in this forum post: Running PLECS blockset model with a smaller time step than the Simulink fixed time step - #2 by Bryan_Lieblick.

Your test model shows the issue in is not due to the mixed-step nature of your simulation. Rather it is solver/circuit related, which sometimes requires a mix of expertise/intuition to resolve. In fact, if you replace your Simulink blocks with PLECS equivalents and run the simulation model you’ll get the same zero crossing error in PLECS Blockset (PLECS Standalone works fine).

I suspect the main driver is that the “Relative Tolerance” value might be set too low such that it actually induces the excessive zero crossings in the output diode rectifier. Relaxing the current value of 1e-7 to something like 1e-5 allows the simulation to complete without the error message. The simulation also runs faster, with a negligible loss in accuracy. You can always use the Refine Factor setting to improve the waveform “shapes” while still maintaining the same level of solver accuracy.

Simply changing the relative tolerance allows one to simulate the undamped circuit (with R_Uin and R_Cr retained to eliminate state-source dependency errors).