Hi.
With the new update of the solver (Nanostep solver) can I achieve simulations with a discreditation step size less than 1 microsecond in RTBOX 1?
Thank you all.
Dear Jose,
yes, on top of the 1xCPU core for simulation you will have a dedicated nanostep solver running on the FPGA. What you run on the nanostep solver will be calculated with a step size of 7.5ns. However, not every component can be executed in the nanostep solver, only specific topologies that we will provide in the PLECS library (e.g buck/boost, DABs, LLC, CLLLC, 3ph inverters, among many others).
If you have a specific topology in mind you can let us know.
