PLECS Coder block execution order in generated code (graphical order vs. signal dependency)

[Parth]

Hello,

I am using PLECS Coder to generate embedded C code for a digital power converter controller (typical chain: ADC acquisition → Clarke/Park transforms → current controllers with decoupling/feedforward → inverse transform → duty cycle and PWM update). I want to understand how PLECS determines the execution order of blocks in the generated code inside a single control task.

In my schematic, there are multiple parallel paths (for example d axis and q axis control, feedforward paths, limiters, software protection and a final modulator).

My questions:

Is block execution order determined by the schematic layout (top block first, then bottom), or is it determined by signal dependency (directed acyclic graph scheduling based on upstream inputs)?

1. If it is dependency based, what happens when there are:

• Multiple signals converging at a summation or selector, where different branches have different intermediate computations?

2. How does the scheduler treat hierarchy?

• Does subsystem order matter?

3. When multiple blocks are independent (no dependency), does PLECS apply a deterministic tie break rule (for example by block ID, creation order, or layout)?
4. What is the recommended way to enforce a required computation sequence if needed?

I am asking because I want to guarantee a specific computation chain.

Thank you.

[Bryan_Lieblick]

Is block execution order determined by the schematic layout (top block first, then bottom), or is it determined by signal dependency (directed acyclic graph scheduling based on upstream inputs)?

See the “Block Sorting” section of the PLECS User Manual or Online Help. The relevant excerpts are at the bottom of the post.

In addition the type of subsystem as well as multi-tasking configuration can also influence the execution order. See the discussion of Virtual and Atomic Subsystems below which describes the different types of subsystems. Also refer to the Code Generation + Task Transitions in Multi-Tasking Mode section of the PLECS documentation.

Algebraic loops also factor into block ordering, but the PLECS Coder does not support code generation for algebraic loops this does not merit further discussion in this context.

Multiple signals converging at a summation or selector, where different branches have different intermediate computations?

Outside of block sorting constraints, one cannot guarantee the calculation order of any intermediate computations. The reason is that the PLECS Coder performs expression folding. Multiple block computations can be collapsed into a single line of code instead of generating separate statements and temporary variables for each block. This makes the generated code more efficient since intermediate local variables and associated memory storage are eliminated.

How does the scheduler treat hierarchy? Does subsystem order matter?

The subsystem’s contents, connection sequence, and type (virtual vs. atomic) matter, but not in which order they are visually arranged in the schematic.

When multiple blocks are independent (no dependency), does PLECS apply a deterministic tie break rule (for example by block ID, creation order, or layout)?

Creation order.

What is the recommended way to enforce a required computation sequence if needed?
I am asking because I want to guarantee a specific computation chain.

Can you explain the reasoning why you need a specific computation chain? Have you observed any behavior that you believe is due to the block ordering? Note the only actuation signal in your model is the PWM block which is shadowed and will only update at the carrier overflow/underflow depending on the block configuration.

You can tweak the behavior by using Atomic Subsystems or adding in delays to break the Direct Feedthrough dependencies and then inspect the impact on the generated code. However, if you need complete control for a critical logic that is not subject to change for a small modification in your model, then write a C-Script.