Dear experts,
Recently, I encountered a problem while using components of RTBox.
I tried to output the same result using PWM out and Digital out, but I found that their output results are different. There is a phase shift between the two, and this phase shift increases over time.
I tried to enter the interior of PWM Out and found that the carrier inside would gradually shift over time. Why is this?
Thanks in advance
Best regards,
zhihao chen
The PWM generation is based on a 133.33 MHz clock (RT Box 1/CE) or 150 MHz clock (RT Box 2/3). The PWM period is calculated in clock ticks, so the PWM frequency is rounded up or down to match the closest number of clock ticks. Each PWM period has the same number of clock ticks.
The CPU step time, on the other hand, is adjusted so that on average it matches the selected step size as closely as possible. Expressed in FPGA clock ticks, the number of FPGA clock ticks per CPU step may vary from one CPU step to another. Other settings, e.g. time synchronization between multiple RT boxes, may further influence the number of FPGA clock ticks per CPU step size.
For this reason, a PWM generated by the CPU and a PWM generated in the FPGA may get out of sync over time. If you want to avoid this, enable the option “Synchronization with model step” in the PWM block. This, however, only works if the discretization step time is an integer multiple of the PWM period.
